Xbox 360 CPU Finaly Revealed

[Slay]

Sorry if this is allready posted, here it is from IBM.
http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw09XBoxDesign

 

["Nerve-Damage"]

Sorry if this is allready posted, here it is from IBM.
http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw09XBoxDesign

Nice find........

Sidenote: Should have stated Xbox 360 CPU in thread title, instead of Xbox.

 

[drpepper]

At the thread title: LOL, well it's about time!

It appears that the CPU employs redundant SRAM arrays in the L1 and L2. could this rule the XeCPU out as the possible low yielding chip?

 

[Slay]

ooops i missed the 360 part i guess some mod will fix it soon.

 

[OtakingGX]

Yeah, we've known about the castrated P3 for years now!

 

[AlNom]

could this rule the XeCPU out as the possible low yielding chip?

mm... not quite I don't think.

 

[c0_re]

Is there an equivalent article on Cell at IBM website?

edit forget it found it, thanks

 

[LunchBox]

yaay!!!

finally!!!

i've been waiting for this!!!

*goes and reads it*

 

[robofunk]

I would actually like to learn multi-processing one one of these babies. The debug stuff sounds like it's as good as an Analog Devices Blackfin DSP I used in an assembly class. Nothing like knowing in the state of every register.

 

[wireframe]

Am I blind or is the die area never mentioned?

 

[AlphaWolf]

Am I blind or is the die area never mentioned?

Just the package size that I can see

The physical package of the chip matters, too. A crucial design goal in the CPU of a consumer electronics device is high volume with good yield and comparatively low cost. The package is a 2-2-2 FC-PBGA, measuring 31mm by 31mm.

 

[AlNom]

I wish they had a larger picture of the die. (I just hate it when they think one-to-one scale would be soooo funny with micro/nanotechnology!)

hm... the fact that they didn't put a redundant core in there... they must have really been cutting it close for die space. A fourth core looks like it would have really messed up organization with the other components on that die.

 

[wireframe]

Just the package size that I can see

Oh well. I guess we have to wait a bit longer for that then. Would be interesting to know for all of these "Compare Xenon to Cell" threads.

 

[ralexand]

I wonder how many devs are using the vmx units and/or if its usage is transparent.

 

[Asher]

I wonder how many devs are using the vmx units and/or if its usage is transparent.

The latest IBM compiler, xlc/xlC, has autovectorization code and other optimizations that will try to use VMX128 units when possible. Admittedly, this is a terrible way to gain optimal performance, and I'd imagine the vast majority of developers will use VMX units "by hand", which will give them much better performance.

 

[ralexand]

The latest IBM compiler, xlc/xlC, has autovectorization code and other optimizations that will try to use VMX128 units when possible. Admittedly, this is a terrible way to gain optimal performance, and I'd imagine the vast majority of developers will use VMX units "by hand", which will give them much better performance.

Thanks for the info, Asher.

 

[Alpha_Spartan]

The chip's front-side bus/physical interface has a 21.6GB/second bandwidth, and runs at 5.4GHz

Huh?

 

[Tim]

At the thread title: LOL, well it's about time!

It appears that the CPU employs redundant SRAM arrays in the L1 and L2. could this rule the XeCPU out as the possible low yielding chip?

All modern CPUs has redundant cache lines - no surprise here.

 

[Guden Oden]

Huh?

What?

5.4GHz * 2 bytes/direction * bidirectional = 21.6GB/s. Very straight-forward.

 

[aaronspink]

What?

5.4GHz * 2 bytes/direction * bidirectional = 21.6GB/s. Very straight-forward.

Is it really at 5.4 GT/s? Thats a quite odd multiplier for both Xenon and Xenos.

Aaron Spink
speaking for myself inc.