Does Cell Have Any Other Advantages Over XCPU Other Than FLOPS?

[Asher]

intel and amd will use cell architecture in about 2010, why cell, why not xenon???
ahhh waste my time.

I don't know where you're getting this from or exactly what you're trying to say.

The trend is towards massively parallel CPUs, not necessarily "using the Cell architecture". Intel and AMD will not use Cell, I'll promise you that.

 

[nAo]

What version meant is that Intel and AMD already shown (rather simplicistic) roadmaps targeting CELL-like CPUs with 1 or 2 cores and a lot of 'attached' processors.

 

[DeanoC]

I think DeanoC impllied in another thread that the Cell core had better multithreading, or am I mistaken?

As I don't even know what I implied, I'd be surprised if anybody does

Cell really requires lots of cooperative multitasking (SPU really don't like pre-emptive), so for system with fairly pre-definable work loads (like games) it can work fairly well.

 

[Squeak]

I don't know where you're getting this from or exactly what you're trying to say.

The trend is towards massively parallel CPUs, not necessarily "using the Cell architecture". Intel and AMD will not use Cell, I'll promise you that.

Well some time ago Intel had a some kind of "Roadmap to the Future" slide presentation, where they predicted 360 CPU like of CPUs in the near future and Cell like CPUs some time further down the road IIRC.

 

[Shifty Geezer]

Cell really requires lots of cooperative multitasking (SPU really don't like pre-emptive).

No AmigaDOS for Cell then

 

[one]

As for Intel "many-core" CPU, Hiroshige Goto commentated it in his recent PC Watch article about the press conference of Justin R. Rattner, Intel Senior Fellow, in Tokyo.
http://pc.watch.impress.co.jp/docs/2005/1110/kaigai222.htm
http://pc.watch.impress.co.jp/docs/2005/1108/intel.htm

According to Rattner, Intel will develop many-core CPU with more than 10 cores in 5-10 years. Along with that, they will develop Virtual Transaction Memory for multithread application development. (Transactional memory is very briefly touched in this article about concurrent programming by Microsoft Research BTW)

The organization of cores for many-core CPU is similar to Cell. A many-core CPU has cores with different microarchitectures in it, single-thread-oriented cores and multi-thread-oriented cores. In another implementation, it can contain non-floating-point-oriented cores and floating-point-oriented cores. But unlike completely heterogeneous Cell microprocessor, all cores in Intel many-core CPU share the same homogeneous ISA.

According to Goto, one of the early plans for Cell was also a homogeneous ISA even with a heterogeneous microarchitecture, but it was eventually discarded to gain better performance. Intel is doing the opposite. He speculates Intel is thinking the transition to Java/.NET runtimie environment is rather slow though Intel research their own software layer called Concurrent Run-time. OTOH, Goto speculates again, Sony deals with Transmeta for realtime compilation technology to abstract the heterogeneous ISA.

 

[scooby_dooby]

And Intel plans this for 2010 not 2006 why's that?

Just because the roadmap resembles cell from an extremely high-level, doesn't speak to the effectiveness of CELL as a gaming CPU, nor is it in any way related to CELL.

 

[darkblu]

No AmigaDOS for Cell then

actually Shifty no cpu likes preempting. the difference between now and the amigaDOS days is that the amount of worktime usually wasted in preemptions has grown, well, erm, uhhh, significantly.

 

[Vince]

And Intel plans this for 2010 not 2006 why's that?

Perhaps because Intel isn't designing a processor for a closed platform and needs to worry about relative preformance in legacy x86 applications as well as absolute preformance/watt/dollar. So, it will take some time before lithography advancement allows for a Cell-esque design which allows for the big, bulky, aspects of a conventional processor as well as the attached processors, cache, busses and control.

Just because the roadmap resembles cell from an extremely high-level, doesn't speak to the effectiveness of CELL as a gaming CPU, nor is it in any way related to CELL.

Of course it does. Intel isn't looking that way because it will yeild lesser preformance that other designs for every expended watt, or dollar or transistor. They, like STI, have realized the benefits to such a heterogenious architecture; STI just got the jump on them and was able to impliment it reasonably well in 2004|2005 on 90nm, do in no small part to the fact that the PS3 is a closed platform.

 

[scooby_dooby]

Or they realized there's alot of performance left in conventional multi-core approaches at this point in time?

And we'll see how "reasonably well" they have implemented it when these PS3 games come out, and we can see how the "power of cell" actually translates onto screen, and conversely what it's limitations are.

 

[pixelbox]

Yup, someone has to be designated driver to start with. Probably seemed like a reasonable idea to have that be the PPE in the current design. However there's no real reason this needs to be the case, they could just as well have put one of the SPUs in charge of configuring the system and telling the PPE what to do.

This is all just flannel, certain people trying to convince themselves that the SPUs are somehow crippled or inadequate. The reality is that although they are certainly optimised for vectorised operation (float *or* integer), streaming, and low-memory footprint operations, they are more than capable of pretty much any kind of "general purpose" code you want.



Thanks but I already have 4...

I have to give it to ya. I was starting to believe him. All the stuff he was saying about cell being a average cpu. Where can i find stuff on cell like how it works?

 

[ChryZ]

I have to give it to ya. I was starting to believe him. All the stuff he was saying about cell being a average cpu. Where can i find stuff on cell like how it works?

http://cell.scei.co.jp/index_e.html

 

[Gubbi]

What version meant is that Intel and AMD already shown (rather simplicistic) roadmaps targeting CELL-like CPUs with 1 or 2 cores and a lot of 'attached' processors.

I think that is different though. What Intel and AMD are aiming at is integration of more and more chipset functions to lower total system cost.

PCIe controller, SATA controller, memory controller, cryptographic engine, ethernet+TCP offload, etc (maybe even a baseline graphics core). Stuff that every PC needs (or will need).

Integrating a sizable chunk of silicon (like 1 or 2 SPU like DSPs) and adding the bandwidth to make them useful, just to only have it utilized by a fraction of PC users is not viable IMO.

Cheers
Gubbi

 

[Titanio]

I think DeanoC impllied in another thread that the Cell core had better multithreading, or am I mistaken?

Crytek's CEO, Cevat Yerli, said that. That sparked a debate about the differences between PPE and Xenon multithreading, to which Deano contributed.

 

[Shifty Geezer]

Integrating a sizable chunk of silicon (like 1 or 2 SPU like DSPs) and adding the bandwidth to make them useful, just to only have it utilized by a fraction of PC users is not viable IMO.

I definitely remember seeing the Intel roadmap and they showed central core+peripheral processing units. The diagram I saw had one or more cores in the middle and lots of smaller cores on the outside. Intel are definitely lookng at a Cell like structure for future chips, because as has been said in many analysis's, single super-cores are approaching their limits. The clock barrier is proving more than expected, and the only way to get more performance is to put on the chip more functional units. I suppose these future chips will have x86 functionality, perhaps reduced in single-core perforfmance to save on die space, and augmented with extra processors that'll gradually be added into the software repertoire. Kinda of like how Apple switching to Intel and providing software emulation through Rossetta which (presumably) means later Intel Apples won't run the old PPC software as fast as a PPC Apple, but will run the new software faster because the Intel CPU's are faster. A change in architecture to Cell-like is no different in principle to a change in ISA like Apples. It'll be a transition period from existing single-core x86 to a hybrid, and maybe eventually a phasing out of the large core when legacy support is not needed, a long time down the line?

 

[Gubbi]

It'll be a transition period from existing single-core x86 to a hybrid, and maybe eventually a phasing out of the large core when legacy support is not needed, a long time down the line?

I don't see it coming.

Special purpose Si is dying. Modems went soft-modem, integrated sound (and a good number of stand alone solutions as well) does all the sound processing in the driver on the x86 host CPU (at least for 3D voices), etc. And this trend is not specific to PCs.

Putting special purpose Si on the CPU die makes even less sense. The Si becomes a mill stone around the neck for chip manufactures once you factor in the 88% of PC users that won't ever use the functionality it provides, for those people an extra general purpose core or a chunk of cache memory would have been better.

Only exception is functionality that is common across all PC platforms (chipset functionality).

As for the x86 juggernaught losing momentum: Not a chance. Last year AMD had a conference call with a bunch of slides, one of them showing x86 overhead for an Opteron (decoders etc) was a whopping 4% of the total die. The extra cost of this is easily offset by the massive economies of scale advantage x86 enjoys.

Cheers
Gubbi

 

[ADEX]

Huh? Are you talking about generating them or looking stuff up? I think the time of (simple) look up tables is over (see memory barrier). And table lookups (where you'd want to resolve each entry in your vector independently) are not suited at all for SIMD instructions...

Yea, I thought something along the lines of that as well at first.
The vector permute instruction in AltiVec allows it, (the SPE ISA is similar). It's only on tiny look-ups though, a few hundred bytes at best. It might (should?) be better in the SPEs.

IIRC It's used for colour space conversion and encryption. I haven't the foggiest idea if it'd be any use in games.

 

[Shifty Geezer]

I don't see it coming.

Putting special purpose Si on the CPU die makes even less sense. The Si becomes a mill stone around the neck for chip manufactures once you factor in the 88% of PC users that won't ever use the functionality it provides, for those people an extra general purpose core or a chunk of cache memory would have been better.

I think the idea is adding targetted silicon where it's needed. Back in the day you could buy your integer CPU and a seperate FPU if you were doing float-intensive tasks. The CPU did all the branch and loops and integer calculations, and the FPU was called on to work out the floating point stuff. If you weren't doing float intensive tasks, there was no need to waste money and silicon on including an FPU. These became integrated onto a single chip as the use of float calcs became more prevalent. What was an optional extra became an essential addition.

Looking to the future if processing requirements (media and maths intensive tasks) see a greater need lots of calculation power over generic processing, that'd be better served with several FPUs than several large generic branch-strong cores, no? I can't find the picture or info, but what I saw of Intel showed something like an x86 core with a dozen FPU's or VPU's around the outside, and that makes sense if the workloads it'll be given are float/vector intensive. This depends really on where code is heading, but both STI and MS felt streamed vector processing was important for performance, and this roadmap I saw suggested Intel think that too. In the same way graphics processing is given over to a streamed vector type, and so a steramed vector unit is much faster thana generic processor at those tasks, a processor with streaming vector units will rattle through those tasks more quickly than a generic processor.

 

[Shifty Geezer]

Yea, I thought something along the lines of that as well at first.
The vector permute instruction in AltiVec allows it, (the SPE ISA is similar). It's only on tiny look-ups though, a few hundred bytes at best. It might (should?) be better in the SPEs.

IIRC It's used for colour space conversion and encryption. I haven't the foggiest idea if it'd be any use in games.

Colour space converiosn could be. There's lots of colour artefacts in HD images as a result of working in RGB space. Rendering a separate highlight buffer and combining with the normal buffer by working in HSL space would give better quality.

 

[Carl B]

With all the discussion about it, surprised the roadmap hasn't been posted yet. So here it is: