New PowerVR Tiling Patent Shows up...

[Kristof]

LINK

You need a TIFF viewer for the images...

 

[PrzemKo]

So, how would you call it in just few words? Quasi-deferred rendering? A binning space reductor? I think, that when you turn the vsync off with that kind of accelerator, you'd see changing blocks similar to what we have in broken MPEG streams. Is that right?

 

[Dave Baumann]

I think I'd call it 'meta tiling'.

If I understand it correctly then this is just a method for reducing the geometry ‘binning’ requirements. AFAIK the like of KYRO cannot flush it bin memory until the entire frame is rendered which means that it has to store the geometry information for the current frame that being written to the frame buffer and has to buffer the geometry that is being calculated by the CPU from the next frame – so it will be attempting to store as much as two frames worth of geometry. I think this method is just allowing large chunks of memory to be freed from the first set of geometry once it has finished with those tile so that the next frame geometry can begin to be buffered into it.

 

[Kristof]

So, how would you call it in just few words? Quasi-deferred rendering? A binning space reductor? I think, that when you turn the vsync off with that kind of accelerator, you'd see changing blocks similar to what we have in broken MPEG streams. Is that right?

Well in Single Render Buffer mode thats what happens. PowerVR is the only accelerator that supports front buffer only rendering, in that case it looks like the VSYNC cutline but its not necessary a line, it can be a broken line where some tiles allong the horizontal access have been updated for the new frame and some others have not. On an immediate mode renderer it would look bad, you would have part of the objects in the scene and part of the objects not in the scene. PowerVR always renders completed tiles so it works in single buffer mode.

Anyway thats really irrelavant to this patent. The patent has to do with the memory storage of the geometry binning and how this memory is freed. Rather than work with one huge screen buffer that gets tiles, the screen first get tiled into macro (big) tiles which are then tiled into micro tiles (small). The trick is now that macro tiles memory can be de-allocated as soon as its rendered. This is better than the old system where you had to render the whole screen before the buffers could be freed. Its even possible to render a macro tile even though it does not yet contain all the data, this means that Z data needs to be stored for that subsection of the screen and read back on the second pass (when you add the rest of the geometry). All in all its just a way to store the tiled geometry efficiently. I guess this would be interesting to read for most here given the common claims that storage of the scene data is the problem with tilers. Also note the "compression" blocks in the patent.

But to explain it very simple. Imagine the screen divided into 4 quarters. Geometry is tiled into these buffers. When you start rendering the tiled data you start with the first screen quarter. As soon as this quarter is finished the data stored for that quarter can be deleted and freed for storing future frame data. Compared to the old system this means that storage space is reclaimed much quicker (the old prior practise only reclaims geometry buffers per frame, once the full frame is rendered the memory is freed in one huge block, now this is done in macro blocks) and thus more geometry data can be stored in the same amount of space.

Any cough... I have not yet read the text myself, just looked at the pictures and glanced at some of the text

 

[MfA]

What determines when patent applications are published? (Its obviously not published shortly after filing, and it hasnt been granted yet.)

Personally I think the main usefullness would be to forego fully deferred shading, being able to throw the data away sooner during rendering with fully deferred shading is nice ... but on the whole it only about halves the storage requirements, if its a problem this solution wont be much good for long.

 

[PrzemKo]

There's one more interesting thing: by reducing amount of memory limit to absolute minimum you can effectively "force" immediate mode (good for testing core's raw power). I wonder, what would be the performace characteristics in relation to different values of that limit (for example, on X axis I'd put number of objects stored per tile, and Y value would be something like Q3's FPS score).

 

[Simon F]

Off topic-ish, but it's bizarre how patents get processed out-of-order by the US patent office.

[EDIT]Ahh, I see it's a patent application that's now visible. Hoorah! At last the US patent office is functioning in the same manner as the EPO.[/EDIT]

 

[Ailuros]

I wonder if SA needs to be "called" to comment on something like that.....