Will R580 have 48 shader 'pipes?'

Will R580 have 48 shader fragment 'pipes?'

  • Yes, just like RV530 has 12.

    Votes: 86 60.6%
  • No way, it's just too many trannies.

    Votes: 56 39.4%

  • Total voters
    142
You do realize, I hope, that no chip is going to have near 600 million transistors for a couple of years, right?
 
Chalnoth said:
You do realize, I hope, that no chip is going to have near 600 million transistors for a couple of years, right?

the newest itanium is over 1 billion.. okay, right.. you mean gpu-chips :D
 
Chalnoth said:
You do realize, I hope, that no chip is going to have near 600 million transistors for a couple of years, right?

Well, that was toward the upper end of your range. 500m about a year from now does not strike me as impossible on 80nm.
 
Chalnoth said:
You do realize, I hope, that no chip is going to have near 600 million transistors for a couple of years, right?

My bet is that the first high end DX10 parts will be around 550 milion transistors around a year from now.
 
Yeah but doesn't that particular Itanium have like 24+MB of L3 SRAM on die? This is not really compareable to logic transistors IMO, since from what I understand, SRAM is
- easier to manufacture (structurally regular)
- denser
- consumes much less power
- easier to make defect tolerant

than logic transitors.
 
Chalnoth said:
I'd venture to guess closer to 400-450 million for DX10 next year.

You were in a higher range than that just for R580 a few days ago.

Are you expecting ATI to save transistors going unified? Well, maybe they might at that, but not net I suspect (i.e. I'm guessing they'd still add more units or "stuff" going from R580 to R600).
 
No, I'm suggesting this based upon a few things:
1. Die shrinks are slowing. And as we get smaller, it gets harder and harder to build the processors on the smaller dies. As such, as we move forward we're more likely to see IHV's not increase transistor counts dramatically on their first products for a particular process for reasons of yield.
2. The 80nm shrink should be very closely in-line with when the first DX10 parts should be shipping.
3. We already have the majority of the features that DX10 parts will need, so increases in transistor count on the order of what we have seen in the past are less likely.

In sum, I do expect that the first DX10 parts will be high-end parts targetted to sit at the top end of the scale, with configurations very similar to the parts to be released this coming Spring. That is to say, from ATI I would expect a Xenos-like setup with 48 shader pipelines and 16 texture pipelines, and from nVidia we'll probably get something almost exactly like the upcoming 90nm version of the G70 except with added DX10 features.

So, ATI will save some transistors by getting rid of the vertex pipelines, though both IHV's will have to add some more transistors to support DX10-level functionality. I don't expect to see either IHV really press the 80nm process to larger die sizes until the refresh of these parts.
 
That is to say, from ATI I would expect a Xenos-like setup with 48 shader pipelines and 16 texture pipelines, and from nVidia we'll probably get something almost exactly like the upcoming 90nm version of the G70 except with added DX10 features.

With the only other difference that Xenos with those unit amounts is lower than ~280 M transistors (add an estimated transistor count for logic and ROPs in the daughter die and leave the transistor count for eDRAM out of the equation). Considering the transistor count I expect for R580, I'd say that R600 could with ease be something like a 6* 16-way SIMD core.

As for NV's sollution it's can't be by far not just a G7x + a Geometry Shader, but a whole damn lot more than that. Not as much related to the amount of units, but how they operate in general.
 
Don't forget that the Xenos also lacks a geometry processor, and has no framebuffer compression logic.
 
It also doesn't have that whatever-it-is in the middle-left of the R520 die. The amount of die that thing takes makes most sense to me as a forward-looking element that is expecting to get relatively smaller (as a percentage of the die) right along --and that means way more transistors.

But NV? Heckifino. If my sig turns out right, that could throw a monkey in the wrench in a lot of ways.
 
rwolf said:
I thought Xenos WAS a geometry processor.
Er, well, there are software workarounds to allow geometry processing on the GPU, but I doubt it will be made use of. I don't believe it could directly support the geometry shader idea that we've seen bandied about for DX10.
 
Chalnoth said:
Don't forget that the Xenos also lacks a geometry processor, and has no framebuffer compression logic.
It seems Xenos implements the GS stage of DX10 with a combination of the "Vertex Grouper and Tessellator" and MEMEXPORT.

And I think it's a reasonable guess that R600 will do so, too.

Jawed
 
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