More hits to the heart for the 4 PE's CPU fans (CELL)

Jaws said:
especially the one on the left! :)
He's Yoshio Masubuchi from Toshiba... (Jim Kahle of IBM holding the wafer, the right is Masakazu Suzuoki of SCEI) Bad luck you didn't choose Suzuoki! :LOL:
images765268.jpg
 
Jaws said:
kaigai005.jpg


I wouldn't expect more than one CELL but those three STI guys look suspect, especially the one on the left! :)

The rows on the right have an odd number of chips.
 
MechanizedDeath said:
Which side of the chip has the FlexIO interface? Isn't that on the side with the SPEs? Isn't that the opposite side of that circuit? I can't tell how the chip is oriented, but that's what it looks like to me. Looks like that circuit is on the side with the PPE rather than the SPEs, so it'll be connecting to the memory interface. PEACE.

That's what i've come up with too.

Npl said:
zidane1strife said:
O/T semi-related question.

I forgot, why do they make the wafers round instead of square?

Quality is best in the middle and lower the further you go to the edge, so the Chips on the edges of a square would be the worst. (I think its because the layers are applied by rotating the wafer and droping the liquid in the center)

The photo resist is/was applied by dropping it on the center and spinning the wafer.
<archairScientistMode="On">
I don't think that applying foto resist is one of the more critical steps in the production chain.
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The silicon ingots are cylindrical due to the method used for growning them.
 
90 nm 300mm wafer

160 single core per wafer + strange logic or 80 double core per wafer + strange logic (no one think that it is edram ? ).. ..is a good yeld ?



P4 wafer (300 mm?) 180 cores (130nm)

the P4 at 180 nm was 217mm^2 (55Mtransistor) back in the 2001

the P4 at 130 nm was 131mm^2 (55Mtransistor)


G5 wafer (300 mm?) 175 cores (130nm)

the G5 at 130 nm SOI was 118mm^2 (52Mtransistor)
 

Power Efficient Processor Architecture and The Cell Processor

PDF and slides
it's a very good read, it shows how they went down to the high-frequency, single threaded, software driven (in order, branch and dma hints) route with their SPE design.

EDIT: are there any chances to have ISSCC papers? :)
 
nAo said:
vliw said:
Any chance i can visiting you at work? :LOL:
LOL..yeah..just send your CV ;)

The papers you are searching for, have not been published yet in electronic form and in the first 2 volume of isscc 2005 there no sign about what you are interested in, maybe in march will see something happen.
 
MfA said:
[Well the electronic versions are not out yet ... but dont you have any account left at unibo? ;)
LOL :) No accounts left, sorry ;)
Mmmm...but....is beyond3d in italy?
EHehe..that's an old story, Marco knew how to read IEEE papers through some unibo proxy :)
 
nAo said:

Power Efficient Processor Architecture and The Cell Processor

PDF and slides
it's a very good read, it shows how they went down to the high-frequency, single threaded, software driven (in order, branch and dma hints) route with their SPE design.

EDIT: are there any chances to have ISSCC papers? :)


please send for me these docs, varga1973@axelero.hu
 
Forgive my ignorance, but what's with the dual XDRRAM blocks for each CELL? What's the significance of that?
 
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