Forgive me, I couldn't resist! Just ignore the figures in the above diagram but not the data flows and functional units!
Okay, assume the above CELL chipsets (BE + 4VSs) are going into PS3 and from what we know from various STI patents.
Given the general/flexible stream processing abilities of the above chipsets and assuming they will also be capable of tile/brick based deferred rendering (TBDR). Will the above chipsets in addition be capabale of ALL or SOME of the following real-time pipelines,
OpenGL ES
REYES
GI (Global illumination) e.g. ray/path tracing, photon mapping etc.
If not all of them then please state the obstacle(s) in the above chipsets. Thanks!
PS. Also assume the APUs can access the PUs cache and the eDRAM directly.