This is a little late, but I got around to looking at some pdfs concerning the pins for ddr and ddr2.
In total, unbuffered ddr has 184 pins, while unbuffered ddr2 has 240.
However, most of these extra pins don't necessarily need to be routed through the memory controller.
There are some operational differences between the two memory types, but from my limited comprehension of the literature, the address and command pins that are routed to the CPU are for the most part the same, as the controller doesn't deal with supplying power and ground to the modules.
There are a few features that seem to require a number of new pins, such as the control for On-die termination, and possibly an additional bank address pin for 1 Gbit ddr2 chips. Most of the other differences appear to me to be hidden within the memory controller or handled by some modifications to the control registers on the modules.
It is possible that a few pins could be switched over by the memory controller if it detects ddr2, which sounds doable and is a sight better than having to worry about 128 extra pins if all dimm traces in a dual channel setup went to the cpu.
The differences in voltage and pin numbering would probably necessitate a socket 939b standard, but this could be transparent to the processor, as the motherboard would route the pins as needed.
In total, unbuffered ddr has 184 pins, while unbuffered ddr2 has 240.
However, most of these extra pins don't necessarily need to be routed through the memory controller.
There are some operational differences between the two memory types, but from my limited comprehension of the literature, the address and command pins that are routed to the CPU are for the most part the same, as the controller doesn't deal with supplying power and ground to the modules.
There are a few features that seem to require a number of new pins, such as the control for On-die termination, and possibly an additional bank address pin for 1 Gbit ddr2 chips. Most of the other differences appear to me to be hidden within the memory controller or handled by some modifications to the control registers on the modules.
It is possible that a few pins could be switched over by the memory controller if it detects ddr2, which sounds doable and is a sight better than having to worry about 128 extra pins if all dimm traces in a dual channel setup went to the cpu.
The differences in voltage and pin numbering would probably necessitate a socket 939b standard, but this could be transparent to the processor, as the motherboard would route the pins as needed.
