NVidia Ada Speculation, Rumours and Discussion

[arandomguy]

I've been seeing people bring up the issue of stock piling up, but is that actually the case or are we just comparing it against the situation of the last 2 years or so? The inventory norm prior was actually stock readily available on shelves (real or virtual) even if products were on sale. Having shelves near empty or empty all the time and having to stock track just to buy anything is not actually the norm in terms of inventory levels. So I'm not sure if simply seeing lasting availability being indicative of an inventory glut.

In terms of pricing and supply that seems like a complex situation as well. Pricing for the higher end GPUs and higher end sub models for GPUs (or even some poor low to mid end models) seem like the most problematic given the various factors in play. The lack supply situation changed the value perspective but with given availability how much extra are you really willing to pay say for RTX 3080 12GBs, 3080ti, or 3090/ti over just the 3080 10GB? This is what I've been seeing with price tracking, the poor value models are the ones that have returned to MSRP (or even lower in some cases). The better value set MSRP ones have not, with the RTX 3060ti (the best one on the Nvidia side) being furthest away from MSRP.

Also how many people are willing to pay for high end AiB variants that cost almost as much if not the same or more than the next tier GPU? Or why would you buy say the a "base" AiB variant now that costs the same or more than other better variants?

The above is also relevant to the Nvidia side of the pricing equation. The fact that AiB's seem to have some very large price gaps among their variants at least to me suggests it's not likely that Nvidia is somehow forcing the pricing issue. Even for the RTX 3060 here I'm seeing $50+ ranges (or $100 even in some cases) for AiB pricing. Some AiBs have been seemingly more aggressive in dropping prices than others.

 

[TopSpoiler]

https://twitter.com/i/web/status/1532207096116064256

https://twitter.com/i/web/status/1532208243618918401

Fresh rumors from Kopite

 

[Krteq]

What the heck?

https://twitter.com/i/web/status/1533350037425893376

 

[Krteq]

https://twitter.com/i/web/status/1533782031670603777

 

[trinibwoy]

These power consumption numbers are really concerning. I need a ~100w replacement for my 1650 super but looks like that may never happen.

It’s also not clear why power consumption needs to go so high. Is it necessary to be competitive with RDNA 3?

 

[DegustatoR]

It’s also not clear why power consumption needs to go so high. Is it necessary to be competitive with RDNA 3?

The only reason I can think of is them pushing the clocks really high to minimize the die size because of N5 ("4N"?) costs. But that reason doesn't apply to AD102 which is expected to be of similar size to GA102. So I dunno. Still looks fishy as hell.

A 4060 on N5 consuming more than 3070 should end up with 3080 performance for that to be reasonable from perf/watt point of view.

 

[trinibwoy]

The only reason I can think of is them pushing the clocks really high to minimize the die size because of N5 ("4N"?) costs. But that reason doesn't apply to AD102 which is expected to be of similar size to GA102. So I dunno. Still looks fishy as hell.

A 4060 on N5 consuming more than 3070 should end up with 3080 performance for that to be reasonable from perf/watt point of view.

3080 performance at 3070 power is about a 20% improvement in perf/watt. Not great for a new process and architecture. I hope it’s better than that.

 

[troyan]

The strange thing is that H100 PCIe with 350W is theoretical ~1.9x more effcient than A100 PCIe 300W. With Lovelace nVidia can use ~twice the numbers of transistor over Ampere. So at the same die size there should be a huge performance boost and much better efficiency than 40% or so.

 

[T2098]

The strange thing is that H100 PCIe with 350W is theoretical ~1.9x more effcient than A100 PCIe 300W. With Lovelace nVidia can use ~twice the numbers of transistor over Ampere. So at the same die size there should be a huge performance boost and much better efficiency than 40% or so.

Manufacturers pretty much always have the choice to go wide and slow for higher efficiency when die size allows.

Apple's SoC designs tend to be on the extreme end of this spectrum, as wide as possible, enormous die sizes, high manufacturing costs, low clocks, and maximum efficiency.

Nvidia's old max-Q laptop designs were the same. They absolutely could release every desktop SKU binned/clocked the same as the Max-Q laptop parts and probably gain 20-40% efficiency... but it'll cost you.

TSMC 5nm/N4 isn't going to be cheap per transistor, so depending on what their price target is, that might not be an option. Consumers tend to be a lot more sensitive to performance per dollar than performance per watt.

 

[DegustatoR]

Consumers tend to be a lot more sensitive to performance per dollar than performance per watt.

Sure but it doesn't make any sense for Lovelace to be both a regression in perf/watt and at the same time a regression in perf/price when compared to Ampere. The numbers don't add up so far.

Also I wouldn't exactly call a 120mm^2 Apple M1 die "enormous"...

 

[troyan]

TSMC 5nm/N4 isn't going to be cheap per transistor, so depending on what their price target is, that might not be an option. Consumers tend to be a lot more sensitive to performance per dollar than performance per watt.

How far do you think will nVidia go? Selling a <200mm^2 die with a 128bit interface for >$400? Does this make sense?

 

[neckthrough]

How far do you think will nVidia go? Selling a <200mm^2 die with a 128bit interface for >$400? Does this make sense?

$/xtor is going up. A 200mm^2 die in N4 is quite possibly more expensive than a 400mm^2 die in Samsung 8. So everyone has to squeeze more perf out of the available transistors. From a gamer perspective what matters is the perf being made available at $400, not the die size being used to deliver that performance.

Yeah it sucks if it comes at the expense of power, but I'm not sure many of us have done the napkin math to translate power consumption during gaming hours to per-month wallet costs due to electricity consumption. I know I haven't -- though maybe I should.

 

[Silent_Buddha]

Sure but it doesn't make any sense for Lovelace to be both a regression in perf/watt and at the same time a regression in perf/price when compared to Ampere. The numbers don't add up so far.

Also I wouldn't exactly call a 120mm^2 Apple M1 die "enormous"...

For the M1 sure. The M1 Pro is ~245.92 mm^2 while the M1 Max is ~432.35 mm^2 on TSMC's 5 nm node.

For comparison the Intel 12th gen CPUs are ~162.75 mm^2 (H0 die) and ~215.25 mm^2 (C0 die) on a much larger process node (Intel 10 nm).

I'd say that qualifies as pretty enormous for a CPU/SOC. Granted they spend more area for the GPU but even the XBS-X SOC is only 360.4 mm^2 on TSMC's 7 nm node. I thought that was pretty massive prior to the M1 Max coming out.

Regards,
SB

 

[DegustatoR]

For the M1 sure. The M1 Pro is ~245.92 mm^2 while the M1 Max is ~432.35 mm^2 on TSMC's 5 nm node.

For comparison the Intel 12th gen CPUs are ~162.75 mm^2 (H0 die) and ~215.25 mm^2 (C0 die) on a much larger process node (Intel 10 nm).

I'd say that qualifies as pretty enormous for a CPU/SOC. Granted they spend more area for the GPU but even the XBS-X SOC is only 360.4 mm^2 on TSMC's 7 nm node. I thought that was pretty massive prior to the M1 Max coming out.

Regards,
SB

These SoCs are supposed to be used in high end systems without dGPU though which explains their size. And they are still not the biggest out there.

 

[TopSpoiler]

These power consumption numbers are really concerning. I need a ~100w replacement for my 1650 super but looks like that may never happen.

It’s also not clear why power consumption needs to go so high. Is it necessary to be competitive with RDNA 3?

There was a rumor that mid-lower Ada will use Samsung foundry. I don't think (and don't want) it would happen actually, but who knows..

 

[DegustatoR]

There was a rumor that mid-lower Ada will use Samsung foundry. I don't think (and don't want) it would happen actually, but who knows..

This would make their perf/watt much worse than it would be otherwise though.

 

[JasonLD]

This would make their perf/watt much worse than it would be otherwise though.

Should be better than current Ampere by some though, and it might be all they need for mid-lower range. Volume is more important than actual performance there.

 

[DegustatoR]

Should be better than current Ampere by some though, and it might be all they need for mid-lower range. Volume is more important than actual performance there.

I'm just saying that suggesting than 8N would be better than N5 in perf/watt is wrong.
It does make sense to keep the lower end on a cheaper process - but then you'll have to wonder why even produce new chips there instead of just using the old TU11x and GA107/106 dies on some new products (GTX17xx/RTX35xx whatever).

 

[T2098]

I'm just saying that suggesting than 8N would be better than N5 in perf/watt is wrong.
It does make sense to keep the lower end on a cheaper process - but then you'll have to wonder why even produce new chips there instead of just using the old TU11x and GA107/106 dies on some new products (GTX17xx/RTX35xx whatever).

Depends how much of an architectural leap they're expecting from this generation.
You could have made the same argument late in RDNA1's lifecycle: "Why produce a new chip on the same process when we already have this one?"

Navi 23 manages to outperform Navi 10 with a smaller die, on the same process, and half the external memory bus width, with the cost improvements from lowered component counts and PCB complexity. All signs point to Ada as being Nvidia's architectural leap into tons of on-die cache, just like RDNA2 was.

 

[DegustatoR]

All signs point to Ada as being Nvidia's architectural leap into tons of on-die cache, just like RDNA2 was.

RDNA2's advantages over RDNA1 are hardly due to "tons of on-die cache".