NV40 poll
- Thread starter Geeforcer
- Start date
There is a limit. The chip may:
a) render X pixels per clock full-featured, no matter what.
b) render Y pixels, no filtering, no color, no coffee, so on
What is the right answer a or b? I think X<16<=Y.
Ps I have a feeling to many, "In The Know" people are basing 16x1 on the 32x0 thingy. If a NV35 pipe can process 2 zixels, why a more advanced pipe can't process 4? (well, over simplifying things)
a) render X pixels per clock full-featured, no matter what.
b) render Y pixels, no filtering, no color, no coffee, so on
What is the right answer a or b? I think X<16<=Y.
Ps I have a feeling to many, "In The Know" people are basing 16x1 on the 32x0 thingy. If a NV35 pipe can process 2 zixels, why a more advanced pipe can't process 4? (well, over simplifying things)
vb said:
Yes it could, and it makes sense.
GeForces use 16 pixel Z tiles with 16 checks.
Having 16 Z-updates is a logical upgrade and the max for a tile.
Having only 8 Z-update/clock in the NV3x limits Z-only performance of 4xAA.
So if it's a "2x(4x2 / 16x0)" config it means it's effectively 2 x NV35 pipeline with further enhanced Z update caps.
madshi said:
OK, how can a gpu be both 8x2 and 16x0? In the first case you have 8 pixel pipes with two texel units per pipe, which can render 8x0/1/2. In the second case, you have 16 pixel pipes with 0 texel units attached to each pipe, and you may only render 16 pixels with 0 texels attached per pixel per clock. In other words, when you tell me you have a 16x0 or a 32x0 pipeline organization, you are telling me that you have 0 texel units per pixel pipe, which means--I'm pretty sure--it would be useless as a 3d gpu.
It sounds like people, again, are somehow concluding that a TMU may *double* as a pixel pipe & texel unit, hence a gpu with 8 pixel pipes and 16 TMUs (2 per pipe) may interchangeably use either pixel pipes or TMUs to render as as many as 16 pixels per clock--uh uh--no way...
TMUs are only good for processing texels which get attatched to a pixel which is rendered by a pixel pipe. You cannot use a TMU to render a pixel. For that, you need a pixel pipe. Thus 8x2 may be 8x0, 8x1 or 8x2, but never 16x0. I'd really like to know why a person might disagree with this...?Only thing I can think of is that people are thinking that because an 8x1 architecture can function equivalently to 4x2, that the *reverse* is also true, that 8x1 can be 16x0. But no, because the the number of pixel pipes in a gpu is fixed, and while conditionally the number of pixels per clock rendered may be LESS than that number, it can never be MORE.
So, what gives?...
WaltC said:So, what gives?...
I'm not sure Walt, I do know for about 99.99% certaintity that the nV40 is 16x1...everything else from there I ain't too certain of. (Oh, 'cept for the R420 being 12 pipes is starting to hit about 85% certaintity with me...I should know for sure a little later.)
digitalwanderer said:WaltC said:So, what gives?...
I'm not sure Walt, I do know for about 99.99% certaintity that the nV40 is 16x1...everything else from there I ain't too certain of. (Oh, 'cept for the R420 being 12 pipes is starting to hit about 85% certaintity with me...I should know for sure a little later.)
Well, if it *is* a true 16x1, then it could do 8x2 performance without a problem. But 8x2 can never be 16x0, if you are using the standard terminology, which is that the first number in the description informs on the number of pixel pipes in the gpu. In fact, it's really a mistake, I think, to call 16x1 anything but 16x1, since that is the fixed pixel pipeline organization, and describes the fixed number of TMUs per pixel pipe. If you use that organization to render 8 pixels per clock & 1 texel, and use the other eight TMUs in the other 8 pixel pipes to render only 1 texel each per clock, and you combine the result to equal the performance of an 8x2 gpu, it still does not change the fact that what you've got there is a 16x1 pixel pipeline organization.
So, Dig, I take it you flatly disagree with the INQ's latest revelation that nV40 is an 8x1 or 8x2 gpu...? (I don't disagree or agree, but consider that suggestion more likely, however, as you already know...
)Hyp-X said:
Well believe what you want to believe but I can assure you that whatever was originally supposed to be the Nv30 failed. Logically it makes much more sense that Nvidia were seeking to continue the 4x2 configuration since they ended up with a overclocked 4x2.
Given that they designed a new core in the 5700u when they already had a mid-range part, people are now saying that they're going to drop this 4x1 ATi style architecture and pursue a 8x2 architecture?
A little logic really would go a long way for a lot of people.
Joe DeFuria
Legend
Demirug said:
Sure...but I think the key stiky point there is sometimes. In other words, under what conditions can said pipeline output more than one pixel per clock?
WaltC said:
Yup, I flatly disagree with this Inq story....too many knowledgeable people that I trust are telling me it's 16x1 for me to think any other way.
digitalwanderer said:
You have to remember that the information that they are receiving are leaks by Nvidia. Nvidia also boasted about the NV30+ as having an 8x1 pixel pipeline. So those "In the Know" quotes mean nothing to me right now. Also, ATI leaks nothing so the 12X1 quotes we have been seeing around I consider made up by attention seekers.
When Wavey, Kyle, Anand and others get their excited hands on those cards and post the reviews, we will then know what each card is capable of.
thatdude90210
Regular
Exactly, could just be unofficially, official-misinformation.Dean said:
Joe DeFuria said:
They conditions are part of the pipeline design.
At first you need a rasterisation that is able to output enougt quads per clock to fill the pixelprocessors. On they other side of they pixelprocessor you need enough ports to transfer the information to the ROPs. And for sure you need enough ROPs for the finish.
Lets look at the NV30. The pixelprocessor is able to output 4 Pixel with color and Z Information or 8 Pixel with only Z-Information. I am not sure if there are two Z-calculation units in the pixelprocessor or if nVidia use some parts of the normal color calculation for the 4 additional Z values. After the pixelprocessor they need some addition ROPs. But this ROPs dont need alphatest or alphableding. Only Z and Stencilops are needed.
A more complete "multipixel per pipe" solution is the NV31. In this case we have two pipes with two tmus but 4 ROPs after they pixelprocessor. If they pipeline is used in they doppel pumped modus they rasterisation unit combines two pixel in one. They texturcoordinate from the first pixel is the first coordinate. They second pixel use the second coordinate. The tmus work as normal but at the end of the pixelprocessor pipe both texturvalues are transferd to different ROPs. nVidia use something like this bevor in the NV10.
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