Well, maybe all the quants work-ups predicted that the vast majority of dice would have 3/4 functional quad pipes. That and/or there would be a favourable statistical significance, given the expected yield, in the clockspeed advantage of a 3/4 design vs. a 4/4 one.
We don't have much of an idea as to how the pipeline breaks down into functional blocks. It could well be that the whole architecture is geared towards processing 3 quads with the exception of a certain block of functionality which is duplicated 16 times - not necessarily an entire stage, just something that represents a relatively large proportion of the die and is likely to suffer from manufacturing defects/clock limitation before everything else. They might be using clock gating to turn off the redundant functionality altogther, saving power. It just seems like a good way to get the most out of the yield of a large, high end ASIC.
