How do you conclude that? IC is allowing a 512GB/s 6900XT to compete with a 936GB/s RTX 3090. That seems like more than a little bump to me.
Current Generation Hardware Speculation with a Technical Spin [post GDC 2020] [XBSX, PS5]
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How do you conclude that? IC is allowing a 512GB/s 6900XT to compete with a 936GB/s RTX 3090. That seems like more than a little bump to me.
AbsoluteBeginner
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But its still much easier and straightforward to compare it to XSX, no? You only subtract extra 16bit bus, 1MB of L2 and 16CUs, everything else stays the same.
So 360mm² (XSX die) - 15mm² (bus) - 35mm² (16CU) ~ 310mm².
For example, full Navi 21 has 4MB of L2 cache, so same as PS5, but in your comparison you effectively slashed it to 2MB duo to halving Navi 21.
That means front end and geometry engine area will also stay the same, so you would have to add ~20mm² to that 260mm² value and you would end up with no extra die for IC.
Infinity Cache is very expensive die cost for performance return (in consoles). There is very little need for them with BW they have.
They would make sense in future though as memory on chip will scale down with lower nodes, but mem controllers wont, so its better to spend area on on die memory then additional memory controllers which will add to complexity and wont actually scale well enough.
So 360mm² (XSX die) - 15mm² (bus) - 35mm² (16CU) ~ 310mm².
For example, full Navi 21 has 4MB of L2 cache, so same as PS5, but in your comparison you effectively slashed it to 2MB duo to halving Navi 21.
That means front end and geometry engine area will also stay the same, so you would have to add ~20mm² to that 260mm² value and you would end up with no extra die for IC.
Infinity Cache is very expensive die cost for performance return (in consoles). There is very little need for them with BW they have.
They would make sense in future though as memory on chip will scale down with lower nodes, but mem controllers wont, so its better to spend area on on die memory then additional memory controllers which will add to complexity and wont actually scale well enough.
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This 5 sq mm is enough difference to cover SSD IO logic between XSX and PS5?
Remember, PS5 IO Complex has:
- SRAM, undisclosed amount
- Kraken decompressor
- IO Co-processors
- Cache Scrubbers
- Coherency Engines
- DMA Engines
And don't forget to account for Multimedia logic (could be off-die).
I think Navi21 layout is more comparable to PS5 especially if we are discussing IC, MS clearly took a slightly different route
That's accounted in the 4 extra PHY I added later (30mm2)
Front end scales with SEs no? I assume 4SEs need a beefier front end than 2
Yes im keeping an eye that, this is just a tentative estimate
Need to know navi21 & ps5 i/o block size.
How much would you guesstimate, PS5 whole I/O would take?
D
Deleted member 7537
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Well that was an easy way to make a fool out of myself. I read some days ago a review of the new AMD cards and when they say they compare games with IC on and off, they are confusing IC with SAM... I mean, it takes a couple of seconds to realize how stupid it sounds that you can turn off the L3 cache.
But coming back to the PS5 (or XBSX) side of things, I undestand that having IC gives you higher effective bandwidth (+ lower latency pool of memory) but if you aren't memory bandwidth starved in the beginning, would it matter so much?
Problem I have with that graph is I don't know to what they are comparing it with. What's an example of RDNA2 without IC, did they say anything?
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I assume is the same chip and same bus sans ic
As anything the proof is in the pudding, you can see it allowing to trade blows with nv cards that sport wider memory buses and faster gddr6x chips
If we say PS5s die is 305 sq mm, my estimations leave 15-18 sq mm for:
- SSD IO Complex logic (additional from XSX SSD IO logic)
- SSD IO SRAM
- Multimedia logic (could be off-die)
D
Deleted member 7537
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Yeah, but if that is the case they were comparing it with (probably) a BW starved GPU. What I mean to say is that if AMD would had gone for a wider memory bus, IC would be less relevant. It seems like an ingenious solution to get better performance while... being more energy efficient?
Maybe MS and Sony were give the option to go width a less wide memory config and add IC to their custom design and wasn't considered the best option.
Just speculation from a guy who likes to read about these things. Probably totally wrong.
Yeah no question about that. I was stupidly confused by something that is very straight forward.
AbsoluteBeginner
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I am still wondering why are we not taking XSX as baseline for comparison and then scaling down to 308mm²?
Both are complete SOC compared to Navi 21 (which is also PC GPU with all other additional logics, and some missing) based on RDNA2, Zen 2 and same memory configuration (one having additional 64bit PHY).
Both have 2SEs, one has additional 16CUs. Subtract excess CUs + PHY and you get exactly PS5 die size.
IC is there for couple of reasons IMO
1) In future (5nm, 3nm) on die memory will scale just fine, memory controllers wont
2) BW for 25TF GPU would be in 800-1000GB/s range, which would require 512bit bus. Absolute no go duo to added complexity, die size and energy req
Given that consoles are equiped with 10-12TF GPUs and 448/560GB/s of mem bandwidth, I dont see what advantage would IC hold when die space on these consoles is premium and they are not BW starved. Number one reason, according to AMD, to bring IC was to claw back BW loss from going with narrow bus (which they had to go with since 512bit bus was not realistic on 7nm).
I still doubt IC is complete replacement for wider bus, given that RDNA2 drops a bit as things go 4K, but its certainly looking like nice tradeof.
Both are complete SOC compared to Navi 21 (which is also PC GPU with all other additional logics, and some missing) based on RDNA2, Zen 2 and same memory configuration (one having additional 64bit PHY).
Both have 2SEs, one has additional 16CUs. Subtract excess CUs + PHY and you get exactly PS5 die size.
IC is there for couple of reasons IMO
1) In future (5nm, 3nm) on die memory will scale just fine, memory controllers wont
2) BW for 25TF GPU would be in 800-1000GB/s range, which would require 512bit bus. Absolute no go duo to added complexity, die size and energy req
Given that consoles are equiped with 10-12TF GPUs and 448/560GB/s of mem bandwidth, I dont see what advantage would IC hold when die space on these consoles is premium and they are not BW starved. Number one reason, according to AMD, to bring IC was to claw back BW loss from going with narrow bus (which they had to go with since 512bit bus was not realistic on 7nm).
I still doubt IC is complete replacement for wider bus, given that RDNA2 drops a bit as things go 4K, but its certainly looking like nice tradeof.
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I've already done a comprehensive breakdown using XSX as a baseline. It's interesting to see if the same conclusion is reached with an alternative method.
Not really. It’s one thing to look at 1.4 TF, 32mb of esram and 68 GBs of DDR3 and assume it less performant than 1.8 TF with 176 GBs, it’s another for this circumstance.
You mean where people wont be able to tell difference in blind tests between the two? Mostly correct because most people can't reliably tell the difference between 900p and 1080p.
Also, in general it remains to be seen how things will look 2 years from now when devs have a chance to put to use the new tech and not be shackled to last-gen designs. Both consoles have a good bit of untapped potential going unused today.
People are absolutely welcome to do that, i already saw a pretty good analysis from @j^aws on ree next gen thread using XSX as a baseline. Different perspectives are always helpful to find answers
It just occurred to me the other day to use navi21 as a baseline when i saw its die size which i expected to be much bigger, personally i think navi21 is a better point of comparison to PS5's GPU since its configuration its closer to it than XSX. Especially so when making the case for IC the GPU layout would be optimized around that to make the most efficient use of die space.
As i said previously im not saying im right, im speculating on the posibility which preliminary at least seems plausible and to bring a different perspective
Full disclaimer: I tend to gravitate towards the optimistic outcomes
1) Would absolutely be helpful to bring costs down on a slim revision
2) A 10TF would potentially see much benefit from a smaller IC pool: less cahe->less hits-> lower average bandwidth. Im sure there's a similar sweet spot for smaller 10TF GPU
Could be, in MS case at least we know their design goals didn't leave enough space for IC so they had to make do with a 320bit bus.
In PS5 case we won't know for sure until a die shot or new information is revealed from Sony and/or devs
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MS/Sony wanted to run BC titles at 'twice the performance' - a cache-based solution couldn't reliably achieve that.
However for a theoretical 'pro' edition PS5/XSX then this type of memory solution would seem relevant.
AbsoluteBeginner
Regular
Generally console SOC are designed around most efficient use of die space per default, I dont think you will see Sony or MS having even low single digit advantage in layout and packaging of components on SOC. Tbh AMD designed all their chips for maximum die space efficiency, as costs on 7nm node are so high per mm² compared to 16nm and 28nm.
Die space is number one requirement for any design, especially console, as SOC is biggest part of BOM, especially at 7nm.
In your example Sony would have big advantage in CU/core per mm² (we are talking about ~20-30mm²) which seems very unrealistic.
I also dont understand what do you mean about Navi 21 layout being closer to PS5.
I think they mean rectangle instead of square for the entirety of the final SOC shape.
Ps5 thermals full review; I hope they come back again when internal SSD expansion is available curious to see how that will play out, but some interesting bits here.
Summary: memory running very hot. soc running warmish reading from the backside of soc, but they aren’t really sure. Mid 70s backside is warm imo. But w/e. It’s not going to get any hotter with power being limited. Only dust could make it worse.
200W power limit. Runs cooler with fins removed.
Menu is about 100W.
Hmm. Looks like I was beaten to the post here. Lol. Should have figured waking up late compared to EU
Summary: memory running very hot. soc running warmish reading from the backside of soc, but they aren’t really sure. Mid 70s backside is warm imo. But w/e. It’s not going to get any hotter with power being limited. Only dust could make it worse.
200W power limit. Runs cooler with fins removed.
Menu is about 100W.
Hmm. Looks like I was beaten to the post here. Lol. Should have figured waking up late compared to EU
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AbsoluteBeginner
Regular
What does that have to do with packaging efficiency though? PS4Pro is longer rectangle and XBX is squarish but both are based on same Polaris chip. Obviously there will be difference in die dimensions when one has extra CUs and 64bit bus, but its not gonna result in lowered packaging efficiency (especially suggested 20-30m² which is insane).
Basically in this case PS5 would be 52mm² smaller but with 32-64MB of additional memory on die with same amount of SEs, Zen 2 cores and literally everything else bar 64bit PHY and 16CUs (which are ~2mm² each). Does not fit at all.
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Definitely warmer then i'd like to have in a pc build. On the other hand i dont think those temps are 'dangerously high'. Ram does run hotter then other parts mostly.
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