AMD: Navi Speculation, Rumours and Discussion [2019-2020]

[Jawed]

Lots of good stuff:

* caches, buffers got buffed (but not that single 128MB cache...) - even Vega 10 contained 45MB of SRAM for some reason

Yes. AMD has in the past referred to "total memory on die" in marketing materials. 128MB of total memory on this die shouldn't be that hard to get to if you merely double Navi 10. Adding a bit more for larger L1s and L2s would make total memory well-hidden in the XBox Series X die shot, for example.

Though we still have a serious problem with the die being so massive, in that case. The total GPU area of XSX is about 270mm² if it were converted to a discrete GPU for PCs. This is including MCs, PHYs and other IO stuff, which adds up to about 100mm² on the Navi 10 die.

It seems we're left with "PS5 die shot has been hidden because it contains the same awesome sauce as Navi 21".

* the chip really contains both HBM + GDDR memory interfaces for some weird (AMDish) reason

The shape of the die as posted earlier looks "optimised" for HBM stacks to run down one or both sides.

If AMD makes an HBM based 64GB "professional" card based upon big Navi, you heard it here first

Or, this could be that rumoured 128 CU, HBM only CDNA chip? But, in the video, measurements were derived both from the size of the PCI Express interface and the size of the GDDR6 memory chips. So that's no good.

Btw the 80CUs is nearly given. It's doubled the Navi10, which is nice and round. Every single opensource mention points to 80CUs. All the leakz so far pont to 80CUs for the top config.

A single patch makes all those leaks redundant 15 lines of code?

 

[szatkus]

Yes. AMD has in the past referred to "total memory on die" in marketing materials. 128MB of total memory on this die shouldn't be that hard to get to if you merely double Navi 10. Adding a bit more for larger L1s and L2s would make total memory well-hidden in the XBox Series X die shot, for example.

I don't know how you came up with this. The largest cache on Navi 10 is L2 and it's just 4MB.

 

[Jawed]

I don't know how you came up with this. The largest cache on Navi 10 is L2 and it's just 4MB.

There's loads of memory on die outside of L2 For example register files.

 

[Leoneazzurro5]

Infinity cache is real (as a trademark at least)
https://trademarks.justia.com/902/22/amd-infinity-90222772.html

https://twitter.com/i/web/status/1313106136443219969

 

[Krteq]

Can't wait for RDNA 2 whitepaper

 

[dumbo11]

20TF shouldn't be too far off from the RTX 3080. Even though that is advertised as being a ~30TF card, it is closer to a 20TF card if it was the Turing architecture. Ampere's TFs are quite inefficient compared to Turing.

As for the 20CUs being used for RT, I don't see why they would equip some CUs with BVH acceleration and not others. So if this is true, it is most likely a baseline setting in the driver which could be changed game to game. I suspect you can't let the code run wild on both rasterization and RT but that it needs some sort of workload allocation.

There are a few possible answers, the simplest one being that they are 'recommending' 20 CUs are used for this.

Another option that their dynamic shared cache-thing scales up to 20 CUs (which is described in the patent as L1, but mentions in an off-hand way that it can be applied to other layers like L2 or even L0).

 

[BRiT]

Infinity cache is real (as a trademark at least)
https://trademarks.justia.com/902/22/amd-infinity-90222772.html

Or the folks at AMD heard of it from the rumors and thought it might be a good name to use in the future, so grabbed it now.

 

[dumbo11]

Or the folks at AMD heard of it from the rumors and thought it might be a good name to use in the future, so grabbed it now.

Lol. But the application was filed in September 2019, so it seems to be an actual thing.

Edit: 2020 actually, doh!

 

[Geeforcer]

Or the folks at AMD heard of it from the rumors and thought it might be a good name to use in the future, so grabbed it now.

Filing Date 2020-09-29

Yeah, seems a little too close to the wire...

 

[jacozz]

Have you guys seen this?

pdf:
https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf

 

[pTmdfx]

Have you guys seen this?

pdf:
https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf

The paper was briefly discussed a week or two ago in the thread, if you want to have a look.

 

[Deleted member 13524]

Infinity cache is real (as a trademark at least)
https://trademarks.justia.com/902/22/amd-infinity-90222772.html

https://twitter.com/i/web/status/1313106136443219969

So the rumor/leak started by the random youtube channel called totally-not-redgamingtech is turning out to be true once again?

On a completely unrelated note, on his last non-video, totally-not-Paul from totally-not-redgamingtech mentioned the following points:

- Navi 21 will not be clocked above its optimal power/frequency curve. This means that the leaked 2200MHz are leaving overclocking headroom. This is being done because a) the performance at 2200MHz is deemed sufficient for competitive performance, b) power efficiency in reviews will be well over the promised 1.5x RDNA1 and c) the OEMs like this because they can then launch 3rd-party cards with higher differentiation (i.e. factory-overclocked cards they can charge more money for). This is pretty much what we saw with Pascal.

- Infinity Cache, which was first mentioned by him, is real and he now claims >99% certainty of this. Which the recent scientific articles and patent requests have all but confirmed anyway. Also confirmed is the relatively narrow 256bit GDDR6 on Navi 21.

- The chip picture leaked by Coreteks may be real, but the measurements they made are wrong, and the chip is smaller than 536mm^2.

 

[SimBy]

Or the folks at AMD heard of it from the rumors and thought it might be a good name to use in the future, so grabbed it now.

You know what, the more I think about it the less outlandish this sounds We know RTG folks on AMD subreddit saw this rumor and someone even left a comment with ambiguous !!!. They probably called this thing something else internally and then marketing guys saw this and were like, guys this sounds way better than what we came up with! Trademark this shit pronto!

 

[Esrever]

Or the folks at AMD heard of it from the rumors and thought it might be a good name to use in the future, so grabbed it now.

I can imagine AMD desperately editing all the marketing material to put it in before Oct 8th now.

 

[Deleted member 13524]

I can imagine AMD desperately editing all the marketing material to put it in before Oct 8th now.

RDNA2 aren't being formally announced before October 28th.. :/

 

[LordEC911]

I can imagine AMD desperately editing all the marketing material to put it in before Oct 8th now.

Find and replace is really useful.

 

[Esrever]

RDNA2 aren't being formally announced before October 28th.. :/

We don't know if infinity cache is for GPU or CPU or both *shrug*

 

[SimBy]

Intels Iris Pro had 128MB L4 cache, but it was on a separate die. Does this not sound very similar to what AMD is trying to do here?

 

[Love_In_Rio]

RDNA2 aren't being formally announced before October 28th.. :/

Well, trademarking it before would have given more clues about it being real, right?.
The same happens with PS5 and no mentions about VRS or mesh shaders. I always thought the real cause was Nvidia, as they are waiting for AMD to make its presentation, so that Sony and devs can after that be more open about PS5's tech.

 

[Rootax]

Intels Iris Pro had 128MB L4 cache, but it was on a separate die. Does this not sound very similar to what AMD is trying to do here?

I guess, if true, that they really tweak this cache to be efficient in a modern gpu context, to save external bandwitdh and increase perfs. Iris felt like a "why not adding more cache" situation to me at the time.