Baseless Next Generation Rumors with no Technical Merits [post E3 2019, pre GDC 2020] [XBSX, PS5]

[anexanhume]

On contrary, it pretty much points to 320bit bus. Theoretical for both Arden and Ariel seem to be using 14Gbps RAM modules, therefore 560GB/s would point at 320bit bus with 14Gbps RAM modules.

View attachment 3623

As we have seen with Oberon, theoretical value for BW does not mean you cannot go higher if there are higher clocked RAM chips out there (which Flute and Oberon tests both confirm).

How is 528 GB/s obviously 256-bit but 560 GB/s is obviously 320-bit?

Also, nice to see my memory chart is being used by others

Here's the whole thing:

 

[AbsoluteBeginner]

How is 528 GB/s obviously 256-bit but 560 GB/s is obviously 320-bit?

Also, nice to see my memory chart is being used by others

Because theoretical values for Oberon is 448GB/s, while for Arden its 560GB/s. This points to AMD using 14Gbps modules to calculate theoretical value, but usage of higher clocked memory would not be surprising, thus value measured would be higher (and since only Oberon was measured, in Github and Flute, its higher then 448GB/s. For Arden, there is only theoretical template - therefore 560GB/s).

Now, both of these can overlap (with 256bit bus anywhere from 448 to 576GB/s), but I think they will not use highest clocked memory available - hence down-clocking (528GB/s would coincidentally point to 16.5Gbps).

Oh, and in case of Oberon there is another tidbit pointing at 256 bit bus :

MEM_NUM_CH=16
MEM_CH_WIDTH_BITS=16

It also says

MEM_DATA_RATE=8

...Could this point to clamshell mode?

BTW great chart! Didn't know it was yours

 

[anexanhume]

Because theoretical values for Oberon is 448GB/s, while for Arden its 560GB/s. This points to AMD using 14Gbps modules to calculate theoretical value, but usage of higher clocked memory would not be surprising, thus value measured would be higher (and since only Oberon was measured, in Github and Flute, its higher then 448GB/s. For Arden, there is only theoretical template - therefore 560GB/s).

Now, both of these can overlap (with 256bit bus anywhere from 448 to 576GB/s), but I think they will not use highest clocked memory available - hence down-clocking (528GB/s would coincidentally point to 16.5Gbps).

Oh, and in case of Oberon there is another tidbit pointing at 256 bit bus :


BTW great chart! Didn't know it was yours

Ok, I see you were starting from the 14Gbps module now. I was trying to ask how you'd reconcile the 528Gb/s and 560Gb/s numbers.

Several people already thought there might be 10 chips based on the Scarlett video at E3, including @Proelite

 

[AbsoluteBeginner]

Ok, I see you were starting from the 14Gbps module now. I was trying to ask how you'd reconcile the 528Gb/s and 560Gb/s numbers.

Several people already thought there might be 10 chips based on the Scarlett video at E3, including @Proelite

Not sure I get you.

528GB/s is measured number from Flute and Oberon (there is a difference in few GB/s and I am not sure if Userbenchmark calculates them right)
448GB/s is theoretical max for Oberon in Github (14Gbps on 256 bit bus)
560GB/s is theoretical max for Arden in Github (14Gbps on 320 bit bus)

Since only alleged PS5 is measured (Flute and Oberon), and there is no measured value for Arden, there is no reconciliation with 528GB/s.

As for XSX E3 reveal yes, it indeed shown 10 chips, therefore pointing at 320bit bus. Oberon and Flute both show 16 chips, therefore confirming 256bit bus.

 

[Mitchings]

I think the PS5 chips in the github leaks were never intended to be production chips, but were simply used for ballpark BC testing while RDNA2 silicon in the appropriate configuration wasn't available.

 

[Xbat]

I think the PS5 chips in the github leaks were never intended to be production chips, but were simply used for ballpark BC testing while RDNA2 silicon in the appropriate configuration wasn't available.

Time for a conspiracy theory why was the Xbox series GPU part ready and the Sony one wasn't during the GitHub leak or are the dates different regarding Oberon and Anaconda during the GitHub test results?

 

[Betanumerical]

Time for a conspiracy theory why was the Xbox series GPU part ready and the Sony one wasn't during the GitHub leak or are the dates different regarding Oberon and Anaconda during the GitHub test results?

The XSX GPU isn't in silicon in the Github leaks its only in a software sim.

 

[N2O]

https://medium.com/auedbaki/amd-ray...en-raytracing-addressed-rx-5600xt-8704575a704

How did we miss this?



So both consoles will have RDNA2 and both will have AMD's ray tracing solution.

Ariel never really fit in with Oberon IMO, and I speculated that Ariel was first Navi (its codename was GFX1000) that Sony needed early to get their BC correctly before AMD had RT and VRS ready (because we have Ariel tests from December 2018, and it was not actual SOC but GPU).

Entire Github test was regression test done on Oberon chip, and Ariel Spec was used for Native/BC1/BC2 tests hence no RT/VRS.

View attachment 3621

That quote is made up, he didn't said that:
https://www.pcgamesn.com/amd/navi-4k-graphics-card

Not saying PS5 won't be RDNA2, but if you google the quote you will only find "report" from that medium site or techquila site, or a gaf thread.

 

[Globalisateur]

Not sure I get you.

528GB/s is measured number from Flute and Oberon (there is a difference in few GB/s and I am not sure if Userbenchmark calculates them right)
448GB/s is theoretical max for Oberon in Github (14Gbps on 256 bit bus)
560GB/s is theoretical max for Arden in Github (14Gbps on 320 bit bus)

Since only alleged PS5 is measured (Flute and Oberon), and there is no measured value for Arden, there is no reconciliation with 528GB/s.

As for XSX E3 reveal yes, it indeed shown 10 chips, therefore pointing at 320bit bus. Oberon and Flute both show 16 chips, therefore confirming 256bit bus.

528GB/s tested (well actually 529.6 using single chip flute test, while Github is at 530, almost exactly the same tested BW) would mean a higher theoretical max. About 550GB/s theoretical max using the same theoretical / measured numbers for Ariel 448GB/s BW found in Github.

 

[AbsoluteBeginner]

528GB/s tested (well actually 529.6 using single chip flute test, while Github is at 530, almost exactly the same tested BW) would mean a higher theoretical max. About 550GB/s theoretical max using the same theoretical / measured numbers for Ariel 448GB/s BW found in Github.

I think you are missing the point of my post and point is that Oberon is chip with 256 bit bus.

We can conclude that from Flute benchmark, and it lines up perfectly with Oberon test. In addition to that, there is 100% proof of 256 bit bus inside Oberon native config file that says following :

MEM_NUM_CH=16

MEM_CH_WIDTH_BITS=16

Theoretical value in Github is calculated based on bus width and memory speed (which is 14Gbps). Duo to this, theoretical for Oberon is 448GB/s, while for Arden it is 560GB/s.

If theoretical value was calculated using 16Gbps or 18Gbps modules it would look like this :

Oberon : 512Gbps / 576Gbps

Arden : 640Gbps / 720Gbps

So, what AMD used as theoretical value was one thing, but since Sony and MS can go for higher clocked memory, that theoretical value does not have to be max. In case of Oberon/Flute, this would point to using downclocked 18Gbps or o'clocked 16Gbps chips, hence higher measured BW.

 

[Shifty Geezer]

That quote is made up, he didn't said that:
https://www.pcgamesn.com/amd/navi-4k-graphics-card

Are you sure that's the press briefing they're talking about? It's presented as a quote. If it's not verbatim, these sites have seriously failed basic journalism and should be taken to task.

 

[Nisaaru]

The XSX GPU isn't in silicon in the Github leaks its only in a software sim.

I seriously doubt that. Afaik MS does the chip simulation themselves which was mentioned back then when they discussed the X1X development. IMHO these are real range of operation tests to validate samples for Sony/MS.

 

[N2O]

Are you sure that's the press briefing they're talking about? It's presented as a quote. If it's not verbatim, these sites have seriously failed basic journalism and should be taken to task.

Well i would hard to believe only 2 small random site quoting that and every tech/gaming site ignore it.
If it really happens, that's that i guess .

Btw Mitchings#7305 could be right? it may end up indeed RDNA2 9.2TF, or worst case it will be still RDNA 9.2TF with hardware RT, at least that's what i think.

 

[Betanumerical]

I seriously doubt that. Afaik MS does the chip simulation themselves which was mentioned back then when they discussed the X1X development. IMHO these are real range of operation tests to validate samples for Sony/MS.

There are no measured values in silicon for the XSX in the GitHub leaks, only values from something called "compass tree" which appears to be a presilicon testing suite.

 

[AbsoluteBeginner]

There are no measured values in silicon for the XSX in the GitHub leaks, only values from something called "compass tree" which appears to be a presilicon testing suite.

Theoretical values are actually not simulated, they are calculated. There are theoretical, pre silicon and silicon values. Arden has none, Oberon has all 3.

 

[Betanumerical]

Theoretical values are not even simulated, they are calculated. There are theoretical, pre silicon and silicon values. Arden has none, Oberon has all 3.

There are a number of files that have a heading of "Measured value of Compass tree". This appears to be some sort of simulator as it doesn't quite match the theoretical perf but its close.

 

[AbsoluteBeginner]

There are a number of files that have a heading of "Measured value of Compass tree". This appears to be some sort of simulator as it doesn't quite match the theoretical perf but its close.

I am looking at Arden data and there is nothing but theoretical data, perhaps they did pre silicon sim, but there is no data for it in repo.

 

[Betanumerical]

I am looking at Arden data and there is nothing but theoretical data, perhaps they did pre silicon sim, but there is no data for it in repo.

Your looking at the wrong data then its in the Arden_COM_BC1_228_0617 folder.

 

[AbsoluteBeginner]

Your looking at the wrong data then its in the Arden_COM_BC1_228_0617 folder.

Can you post screenshot here, I don't have that file at my work's PC? I can see following columns and only theoretical is filled out.

Theoretical value / Measured value of Soc tree / Measured value of Compass tree / Silicon achieved value

 

[Betanumerical]

Can you post screenshot here, I don't have that file at my work's PC? I can see following columns and only theoretical is filled out.

Theoretical value / Measured value of Soc tree / Measured value of Compass tree / Silicon achieved value