Intel ARC GPUs, Xe Architecture for dGPUs [2018-2022]

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No it didn't, it used standard 4-pin Molex. Voodoo 5 6000 (the one with 4x VSA-100) would have come with a power brick but most if not all of the cards have since been modded to take power from 4-pin Molex instead (it wasn't really THAT power hungry, the PSUs were just crappy at the time so they apparently couldn't trust getting enough 12V out from them, the Voodoo Volts power brick was capable of delivering measly 55,2 watts (12V 4,6A))

500 watts for datacenters and the like, not consumers. DG1 can't be used for any analysis, as it's different chip on different microarchitecture (Xe-LP vs Xe-HP)

So it was, I was being forgetful.
 
I'm not well versed enough to opine on this, but it's interesting.

Notebookcheck: Intel Xe in trouble: Leaked Intel DG1 Sisoft Sandra scores are 51 percent slower than the GTX 1050 Ti
I'd never put much weight on performance numbers on SiSoft leaks.
Also I have no clue why, but for whatever reason no matter how many times Intel has said Xe is in fact 3 microarchitectures, almost every site judging the whole architecture based on Xe-LP chip that (almost certainly) won't be used in any discrete desktop format and is different from Xe-HP which will cover most of the markets.
 
I'd never put much weight on performance numbers on SiSoft leaks.
Also I have no clue why, but for whatever reason no matter how many times Intel has said Xe is in fact 3 microarchitectures, almost every site judging the whole architecture based on Xe-LP chip that (almost certainly) won't be used in any discrete desktop format and is different from Xe-HP which will cover most of the markets.

It's the same architecture, no ?

https://www.pcgamesn.com/intel/xe-microarchitecture-lp-hp-hpc?amp

"It’s all technically the same GPU architecture, but Intel intends on divvying up the functionality and features across the entire product stack."
 
There's 3 "versions" of the architecture each aimed at differing markets, and it's not clear right now exactly what that means.

Yea I still haven't wrapped my head around it. Is Arctic Sounds still around in some form? Is there an expected convergence of design parts between Gen11 and Arctic Sound? Rumours around a clean sheet design to come shortly in the Xe saga by Rajas hand alone from AdoredTV... It's an interesting dumpster fire of rumours and tech confusion.

What jumped out at me was the power draw, which seems insanely high for a modern part of modest performance. Now obviously this is pre-production silicon (one hopes) and might be rough around the edges... but it's on a new process node and derived from a low power consumption Gen11 part. A 1050 ti draws around 70-75 watts maximum, a 14nm Pascal part.
 
Yea I still haven't wrapped my head around it. Is Arctic Sounds still around in some form? Is there an expected convergence of design parts between Gen11 and Arctic Sound? Rumours around a clean sheet design to come shortly in the Xe saga by Rajas hand alone from AdoredTV... It's an interesting dumpster fire of rumours and tech confusion.

What jumped out at me was the power draw, which seems insanely high for a modern part of modest performance. Now obviously this is pre-production silicon (one hopes) and might be rough around the edges... but it's on a new process node and derived from a low power consumption Gen11 part. A 1050 ti draws around 70-75 watts maximum, a 14nm Pascal part.
Arctic Sound is the official code name for Xe-HP-cards (as seen in the leaked datacenter group slides), not sure if it covers Xe-LP or Xe-HPC in any form

As for the SiSoft leak, there's several different things which raise some eyebrows, which more likely means SiSoft reading things wrong than anything else.
The driver name, something which you probably can't read wrong, suggests integrated graphics. This is supported by the DDR4 memory etc.
The rest of it says "960 SPs" and "120 CUs" which do and don't match up. 960 SPs would be 120 "CU's" (EUs) if Xe still has 8 pipes per EU, that matches up.
However, we already know that integrated and Xe-LP are 96 EUs, not 120, and none of the Xe-HPs is expected to be 120 EUs either, but 128, 256 and 512 EUs (which may or may not be comparable to Xe-LP EUs, we don't know yet) for 1, 2 and 4 Tile GPUs
 
There's 3 "versions" of the architecture each aimed at differing markets, and it's not clear right now exactly what that means.

Differentiating with the amount of "Tiles" makes it sound like they are the same architecture. Obviously there will be some features/optimizations saved to differentiate from the lower tier offerings.

new process node ? The dev kit version are using 10nm/7nm ? I believe it was still 14nm+++

I dunno why they would do anything on their current 14nm process. They have 10nm working at some capacity, right?
Even if you are only getting a dozen or so units per wafer, better to debug/optimize on a process closer to what will be released.
 
Differentiating with the amount of "Tiles" makes it sound like they are the same architecture. Obviously there will be some features/optimizations saved to differentiate from the lower tier offerings.
They're not differentiating architectures with amount of Tiles.
Xe-HP has 1 common die, "Tile", and scales with amount of dies. Not sure if it's confirmed or not yet but apparently they should be 128 EUs per die (Tile)
Xe-LP we know for sure having 96 EUs.
We don't know if Xe-LP EU = Xe-HP EU or not.
And Xe-HPC is a whole another story and we don't know if Xe-HPC EU's are similar to either LP or HP EUs

I dunno why they would do anything on their current 14nm process. They have 10nm working at some capacity, right?
10nm is in working capacity, but it can't reach clockspeeds anywhere near 14nm, heck, 10nm Ice Lake is getting it's ass handed to it by 14nm Comet Lake on same TDP in everything but graphics (Ice Lake Gen11, Comet Lake Gen9.5) - despite having higher single thread IPC

edit: was supposed to fix "single core" to "single thread" but fixed it to "thread core" instead. Now it's fixed.
very late edit: Apparently last time I fixed it into "despite having single higher thread IPC". I hope I got it right this time :LOL:
 
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Raja stated that Xe LP is only for iGPUs, as it's max working TDP is 20w, it can scale up to 50w though, but it will be terribly inefficient, so Intel won't do it. So is DG1 Xe LP? or Xe HP?
960 SPs would be 120 "CU's" (EUs) if Xe still has 8 pipes per EU, that matches up.
According to Anand, Xe-HPC is an 8 pipe indeed
it is very easy to see that an Xe-HPC unit has an 8-way outline, which likely indicates 8 threads in parallel if the diagram is an accurate representation
https://www.anandtech.com/show/1518...95xDg-ChwjYMyFBZ60VNPUvNDIqVp-4hHCWzMyzh3DukY
 
Raja stated that Xe LP is only for iGPUs, as it's max working TDP is 20w, it can scale up to 50w though, but it will be terribly inefficient, so Intel won't do it. So is DG1 Xe LP? or Xe HP?
DG1 is Xe-LP, but it's not coming for sale
 
Fixed RT link:

Probably this is what Intel has meant with RT support on their upcoming GPUs. But tells us nothing about realtime or DXR plans.
 
Based on this leak (assuming its true) the Media engine on Xe will support the AV1 Codec
https://videocardz.com/newz/exclusive-intel-rocket-lake-s-features-pci-express-4-0-xe-graphics
Intel-Rocket-Lake-S-VideoCardz-1000x486.jpg
 
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