Hmqgg never verified 64CUs. Also he is not full of shit. He is a game dev with sources at AMD.
Next Generation Hardware Speculation with a Technical Spin [post E3 2019, pre GDC 2020] [XBSX, PS5]
- Thread starter DavidGraham
- Start date
-
- Tags
- john sell
- Status
Hmqgg never verified 64CUs. Also he is not full of shit. He is a game dev with sources at AMD.
This goes against the GitHub leak. It's 56CU active. 3584 operations/simd/clock.
Either they have 4 CUs disabled, or all 56CUs active in retail. Either makes sense to me.
AbsoluteBeginner
Regular
Pretty sure he confirmed 64CU part when Klee said "bingo!"
Edit
Checked, you are right. It was another guy here from B3D actually, but he assumed
Last edited:
That's going to be very expensive. Only perfect chips will be useable. That's AFAIK unheard of, let alone on such a massive slab of silicon.
I'm getting 71% yield on die wafer calculator. Obviously only a portion of that can stable at the required clocks.
I guessing it's a matter of how many of the defective dies can be acceptable for use in Azure / Xcloud, and the volume needed for Azure / Xcloud.
i.e 20 million Xsx SOC fabbed lifetime. 50% are defective. 10 million perfect chips are in the console. ~5-6 million defective chips are used in XCloud / Azure.
Last edited:
Using what calculator and parameters? Maybe I'm out of touch, but that seems optimistic to me. eg.
70% on Zen 2 7nm which is <90 mm². 4x the die size for XBSX should be far worse yields for perfect chips.
AbsoluteBeginner
Regular
Seems overly pessimistic. How bad would that make any die over 200mm² (even Navi 10)?
Here is defect density from TSMC
Its pretty straightforward to get ballpark.
anexanhume
Veteran
This number is (unofficially) supposedly over 85% now. With TSMC's 0.09/cm^2 defect rate, it would be over 90%.
https://caly-technologies.com/die-yield-calculator/
20 width 20 height, 300m wafers, 0.09 defect rate.
AbsoluteBeginner
Regular
Why not use 23*17 from what Phil posted?
71% yield.
https://www.resetera.com/threads/ps...hread-ot9-for-flops-sake.162235/post-28334670
Patent about DS5 haptic usage
Patent about DS5 haptic usage
https://schedule.gdconf.com/session...pu-using-a-procedural-dependency-graph/869182
Seems like Turn10 will use the CPU to help out with RT.
Seems like Turn10 will use the CPU to help out with RT.
Accelerated by hardware CPU Ray Tracing ?
That'll be the key takeway for dummies.
Doesn't World Of Tanks use the CPU to construct the BVH's (Bounding Volume Hierachies)?
Though I'd assume the latency of moving data between CPU<>GPU would be incredibly detrimental to real-time RT? (Perhaps an advantage of an APU?)
Disclaimer: I have an incredibly rudimentary understanding of the hardware underpinnings of how RT is done, so may be way off the mark here...
Though I'd assume the latency of moving data between CPU<>GPU would be incredibly detrimental to real-time RT? (Perhaps an advantage of an APU?)
Disclaimer: I have an incredibly rudimentary understanding of the hardware underpinnings of how RT is done, so may be way off the mark here...
Doesn't World Of Tanks use the CPU to construct the BVH's (Bounding Volume Hierachies)?
Though I'd assume the latency of moving data between CPU<>GPU would be incredibly detrimental to real-time RT? (Perhaps an advantage of an APU?)
Disclaimer: I have an incredibly rudimentary understanding of the hardware underpinnings of how RT is done, so may be way off the mark here...
http://fileadmin.cs.lth.se/graphics/research/papers/2016/rayacc/rayacc.pdf
Sounds they use CPU to select a good distribution of probe positions, likely from a given large set, player position, time of day, open / closed doors... just guessing.
And then use GPU RT to generate cubemaps or SH... for those probes.
Likely very efficient because probes can be reused and need no update every frame for each of them. I guess it's faster than Morgan McGuires dense probe grid but less accurate.
Is it possible for probe selection to use a significant portion of the CPU frame time? i.e. 8ms
- Status
Similar threads
- Locked
