A question not really related to this chart but how do you calculate TF from CU count and clock frequency? Thanks in advance.Credit to DemonCleaner at NeoGAF for his table.
A theoretical 64 CU GPU at 1500 MHz with 10 GDDR6 chips and 3.5GHz Zen 2 APU might draw:
140W GPU
35W/2 memory
50W CPU
TOTAL: 208W
TOTAL AT THE WALL:~260W (18W memory power, 10W SSD, OD, misc, 90% efficient supply)
Next Generation Hardware Speculation with a Technical Spin [post E3 2019, pre GDC 2020] [XBSX, PS5]
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anexanhume
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TF = CU * 64 * 2 * clock
Miniature Kaiju
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Total Shaders * frequency * 2.
Total shaders = shaders per CU (64, in this case) * CUs.
Thanks.
DavidGraham
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No way in hell.
You would think AMD is stupid enough to launch a 40 CU part that consumes 220w when they can launch a 64 CU monster at 140w and clean house at the high end dGPU market leaving NVIDIA in the dust?
People need to set their expectations right.
Physics don't work like that, even a 5500XT can reach 140w, and it's a 20CU part.
anexanhume
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This tells me you didn’t actually read the post.
DavidGraham
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I read and read it well, once more physics don't work like that, a 22 CU part consumes a 130w (5500XT), IMAGINE a 64 CU part.
anexanhume
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Reasons I know you didn’t read the post:
1. You didn’t differentiate between board draw which includes memory, IO, die and VRM efficiency vs. a die only measurement.
2. You didn’t acknowledge the effect of lowered frequency and undervolting to achieve lower power draw.
Both of those points are either implicit or explicit simply from reading the table alone.
DavidGraham
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The estimate of only 140w for the die alone is too low even after you factor in these factors.
I did, and once again, they are never effective to the extent if reducing power draw by this much.
anexanhume
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Nice!Credit to DemonCleaner at NeoGAF for his table.
A theoretical 64 CU GPU at 1500 MHz with 10 GDDR6 chips and 3.5GHz Zen 2 APU might draw:
140W GPU
35W/2 memory
50W CPU
TOTAL: 208W
TOTAL AT THE WALL:~260W (18W memory power, 10W SSD, OD, misc, 90% efficient supply)
I would add a general 5% for VRM losses.
I wonder also if the south bridge might be a lot beefier this time around. Maybe they'll connect the ssd directly in pcie on the soc. So a tiny ARM would still be fine for usbs and odd, etc...
Pcie lanes are not negligible power at these frequencies.
anexanhume
Veteran
That is an excellent point. I’m also very curious about SB and whether or not PS5 stays true unified memory or adds a split pool like Pro for OS and standby tasks.
The OQA leak had 4GB of SSD Cache + 2GB of DDR4. If the leak is true, it's unknown what those 2GB of DDR4 are for.
PS4 already has that. We should talk about unified memory architecture when talking about what developers can use for their games. In that case the only current gen console that is not using a unified memory arch is XB1.
And about PS5 I fully expect them to continue having some DDR for OS tasks. You don't change a formula which works (for them).
anexanhume
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I assume it’s LPDDR4 like the Pro.
That’s right. I always forget the ESRAM breaks the hierarchy. Makes it more impressive that Scorpio is seamlessly compatible.
DavidGraham
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Oh? I must have missed the measurements of the 64 CU part, because I don't see it anywhere.
Once more, if that was possible, AMD would have jumped at the chance of releasing a 64 CU die with the power consumption of 200w or less.
You simply don't know how RDNA scales in power as you increase CU count, but you can partially infer it if you compare 5500XT to 5700XT, 22 CU to 40 CU, an increase of 80% in CU count, yielding an increase of power consumption from 130w to 230w, which is a 76% increase.
Likewise, the move from 40 CU to 64 CU (60% increase) will probably yield a 50% increase in power draw or more.
Your table also assumes a 64 CU will accept the same voltages at 1500MHz as a 40 CU part, which is a grave mistake.
In summary nothing in that table makes sense regarding the topic at hands, except for blind and very optimistic speculation.
Pretty much all of the PCBs I see on a daily basis are blue. Looks like home to me.
anexanhume
Veteran
Your own math suggests there is a mere 5% error in linear scaling from 22 to 40 CUs. I can live with that.
As for voltage scaling, are you suggesting AMD don’t know how to do power plane design and voltage drop analysis?
You also make a ton of assumptions about AMD’s internal decisions when you presume they could have a 64 CU die ready at the same time, have acceptable yields, and would want the market stratification it implies at time. We are talking about a die that will launch 17 months after the one in question.
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It's a better starting point than your reliance on TDP for your arguments. 6 months of process improvements between 5700xt and 5500xt would have shifted the knee of the efficiency curve so TDP limit at max clock is not helping figuring out what happens at the lower clock that falls behind the knee in one case, and above the knee in the other at 1500mhz. The table is helping at least with the modern process improvements, and it charts the clock to efficiency relationship. The TDP ceiling is useless.
If you think it's so off, how many watts do you think a 12TF Navi console will consume from the wall?
He said 260W, I would say more conservatively 280W.
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