AMD Navi Product Reviews and Previews: (5500, 5600 XT, 5700, 5700 XT)

PSman1700 said:
Turing went more compute (and graphics?), Navi the other way around.
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The difference is, Navi was developed from Compute-heavy GCN while NVIDIA has been focusing comparatively more on the graphics side since Kepler or so
 
Polaris lacks fp16, which could eventually affect seen benchmark results.
I never used Polaris, but 2 or 3 older GCN generations. There was no big difference - performance always scaled with CU count and clock as expected.
 
JoeJ said:
Polaris lacks fp16, which could eventually affect seen benchmark results.
I never used Polaris, but 2 or 3 older GCN generations. There was no big difference - performance always scaled with CU count and clock as expected.
Click to expand...
Polaris 30 is ~7 TFlops with 5.7 bln transistors and 225W TBP. That's ~70% of Navi 10 Tflops in ~60% of transistor budget.

Also worth noting that when AMD speak about GCN being better for compute right now they are more than likely mean solely Vega 20 which is 13,8 Tflops with 1/2 FP64 - quite a bit higher than what Navi 10 is capable of. I am 100% sure that this narrative will change as soon as they'll launch an RDNA GPU which will be faster than Vega 20 in peak Flops, at least in FP32.
 
... which would mean GCN is only 'good for compute' because they have larger GCN chips available right now. That's pretty much what i would think too.

Still, seeing GCN going EOL hurts my feelings. :D
 
JoeJ said:
.. which would mean GCN is only 'good for compute' because they have larger GCN chips available right now. That's pretty much what i would think too.
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Well, there are probably some other reasons too, like GCN using narrower SIMDs compared to RDNA and spending relatively less of a die budget on graphical features. But the main reason is likely simple - Vega 20 is faster than Navi 10 in compute right now.
 
Did engineers say that one is more compute and the other more graphics optimized or did marketing bring that up?
 
It's not like gaming, where you have multiple games over time you play and may or may not come across one that uses RTX. Most companies have their software ecosystem which does what they need it for and yes, if that happens to support raytracing and has an optix backend, then Quadro is a good choice. If it does not use raytracing and/or has no rtx interface, then you buy based on perf and cost in YOUR application.
 
192-bit bus mean 6x 32 bit GDDR6 memory controllers. Highly likely there is a 30 CU part in the 5600-series, but if the 5600-series is a cut down Navi 10 e.g. Navi10LE it could go as high as 36 CU in steps of two, though unlikely. From a business prospective I doubt 36 CU due to cannibalization of RX 5700 @ 1080p, 1440p.

The max so far seen for Navi 10 is 5 WGP per 32-bit memory controller, Navi 14 has 3 WGP per controller. If this is Navi 12 then could be at 4 WGP per controller resulting in 32 CU for Navi 12. But an extra Chip in between 158 mm^2 and 251 mm^2? I doubt that makes much sense strategically from yields, wafer costs and the amount of wafers AMD can use at TMSC right now.

I'm strongly leaning towards this being a cut down part...
 
PizzaKoma said:
192-bit bus mean 6x 32 bit GDDR6 memory controllers. Highly likely there is a 30 CU part in the 5600-series, but if the 5600-series is a cut down Navi 10 e.g. Navi10LE it could go as high as 36 CU in steps of two, though unlikely. From a business prospective I doubt 36 CU due to cannibalization of RX 5700 @ 1080p, 1440p.

The max so far seen for Navi 10 is 5 WGP per 32-bit memory controller, Navi 14 has 3 WGP per controller. If this is Navi 12 then could be at 4 WGP per controller resulting in 32 CU for Navi 12. But an extra Chip in between 158 mm^2 and 251 mm^2? I doubt that makes much sense strategically from yields, wafer costs and the amount of wafers AMD can use at TMSC right now.

I'm strongly leaning towards this being a cut down part...
Click to expand...
They're actually 16bit memory controllers
 
PizzaKoma said:
Can they be decoupled from two (16+16-bit) channel though, from any practical standpoint? As far as I've read on GDDR 6 they can't, they can be joined in pseudo channel mode with penalty. But I am not an engineer by trade. So even if one channel is 16-bit, the bus-width of the controller to the memory module is 2x16-bit aka 32-bit
https://www.jedec.org/standards-documents/docs/jesd250b
Click to expand...
If anything it would probably be 4x16bit grouped as 64-bit since AMD uses 64-bit on highest level block diagram. But regardless of that, they list 16 MC's (x16 = 256bit) in RDNA Cache hierarchy -slide.
 
Navi10 dieshot from AMD HotChips slide
DxCp1Be.jpg
 
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