Next Generation Hardware Speculation with a Technical Spin [post E3 2019, pre GDC 2020] [XBSX, PS5]

[chris1515]

During an interview Crystal Dynamics said there will be PS5 improvement for Marvel Avengers

 

[Deleted member 13524]

During an interview Crystal Dynamics said there will be PS5 improvement for Marvel Avengers

What's the timestamp for the mention on PS5 improvements?
I'm way too distracted by the humongous golden... thing.. wrapped around that guy's chest. (I mean.. why? That's either metal and painful to wear or a lot of plastic.)

 

[chris1515]

What's the timestamp for the mention on PS5 improvements?
I'm way too distracted by the humongous golden... thing.. wrapped around that guy's chest. (I mean.. why? That's either metal and painful to wear or a lot of plastic.)

No idea I did not see the video.

 

[anexanhume]

It seems Sony is concerned about Spectre exploits too.

http://www.freepatentsonline.com/WO2019199544A1.html

 

[bbot]

Recently, there has been a rumor that Oberon's (PS5 SoC) die size is 300mm^2. If we assume 40CU/36CU (devkit/retail), then would there be enough space left over on the die for dedicated RT cores?

 

[iroboto]

Recently, there has been a rumor that Oberon's (PS5 SoC) die size is 300mm^2. If we assume 40CU/36CU (devkit/retail), then would there be enough space left over on the die for dedicated RT cores?

I don't think there is any strong evidence to suggest RT cores take up a lot of silicon. Tensorcores on the other hand could.

 

[Proelite]

Recently, there has been a rumor that Oberon's (PS5 SoC) die size is 300mm^2. If we assume 40CU/36CU (devkit/retail), then would there be enough space left over on the die for dedicated RT cores?

The retail PS5 is most likely 40CUs. Komachi leaked that the PS4 bc mode is 18CU and the PS4 Pro bc mode is 40CU. The Ps4 pro sdk probably prohibited devs from locking to using 36CUs for pro, thus they can have BC for PS4 pro uses all 40CUs on the PS5.

Had the PS4 pro BC mode use 36CUs, then I wouldn't be so sure about the CU count. Put it this way, if the PS4 Pro bc mode uses 40CU and if PS5 has more than 40CUs, why wouldn't the BC mode use more than 40CUs?

40CU lines up with the same customization strategy Sony did for the Pro, take the best mid-range AMD GPU at the time and add some extra defective CUs for binning.

RX 480: 36CUs. All active.
PS4 Pro: 40CUs. 36 active.

Navi 10 XT: 40CUs. All active.
PS5: >=44 CUs. 40 active.

Oberon devkit is 40CU at 2.0ghz for 10.24 teraflops.
Retail might be same or lower clocked.

DISCLAIMER: DISREGARD ABOVE IF YOU DON'T TRUST KOMACHI ENSAKA-SAN

 

[metacore]

Here it is.

edit, looks like different radiators on both side of V. One for soc other for psu? ...or one for cpu chiplet and second for gpu

 

[PSman1700]

Damn that looks big? Don't think the final product is gonna look like that.

 

[AbsoluteBeginner]

Damn that looks big? Don't think the final product is gonna look like that.

Obviously wont, looks ugly as sin. PS4 dev kits where big as well so it might be a norm.

 

[Proelite]

Here it is.

edit, looks like different radiators on both side of V. One for soc other for psu? ...or one for cpu chiplet and second for gpu

cpu and gpu shouldn't be that far from each other. That's a lot of wasted power and increased latency for some extra ease of cooling.

 

[PSman1700]

Obviously wont, looks ugly as sin. PS4 dev kits where big as well so it might be a norm.

When i saw sketches of that V devkit i kinda liked it, but nevermind seeing the real thing now

 

[metacore]

cpu and gpu shouldn't be that far from each other. That's a lot of wasted power and increased latency for some extra ease of cooling.

Certainly, but in such design cpu/gpu themselves should probably be closer somewhere in center under mounting with heatpipes connecting to radiators on sides. Ohh Dreams of chiplets...

 

[McHuj]

Pics of devkits but no TF numbers!?!?!? WTF?!?!

 

[chris1515]

From this video

 

[iroboto]

cpu and gpu shouldn't be that far from each other. That's a lot of wasted power and increased latency for some extra ease of cooling.

Might just be a design feature. Without knowing what’s under the cover it’s hard to say.

 

[Tkumpathenurpahl]

Maybe it utilises the strange heatsink patent that we've seen?

For example:

• on the right hand side is contained the SoC with the main heatsink on the top. The vents on the right feed and expel the air for said heatsink.
• on the left hand side is contained the PSU. The vents on the left feed the PSU, and also circulates to feed the bottom heatsink of the SoC.

Also, might that patent be a means of providing adequate bandwidth between two GPU chiplets or SoC's? IIRC EMIB requires a fair amount of power, and therefore cooling, in order to provide adequate bandwidth for GPU chiplets. Those chiplets could be cooled with a traditional heatsink, whilst the interconnect is cooled from beneath.

This could be a means of binning for 3 different consoles:

• Use 40CU chiplets. Disable 4 for redundancy.
• Those with the best thermal profile at the highest clocks are paired up for a PS5Pro.
• Those with a worse thermal profile at the same or lower clocks are separated for a base PS5.
• Those which can't reach adequate speeds could be binned for a PS4Pro Slim.

Manufacturing would improve over the years, and the PS4Pro Slim chips could be phased out, but it's at least a means of selling otherwise junk chips in the first year or two.

 

[anexanhume]

Maybe it utilises the strange heatsink patent that we've seen?

For example:

• on the right hand side is contained the SoC with the main heatsink on the top. The vents on the right feed and expel the air for said heatsink.
• on the left hand side is contained the PSU. The vents on the left feed the PSU, and also circulates to feed the bottom heatsink of the SoC.

Also, might that patent be a means of providing adequate bandwidth between two GPU chiplets or SoC's? IIRC EMIB requires a fair amount of power, and therefore cooling, in order to provide adequate bandwidth for GPU chiplets. Those chiplets could be cooled with a traditional heatsink, whilst the interconnect is cooled from beneath.

This could be a means of binning for 3 different consoles:

• Use 40CU chiplets. Disable 4 for redundancy.
• Those with the best thermal profile at the highest clocks are paired up for a PS5Pro.
• Those with a worse thermal profile at the same or lower clocks are separated for a base PS5.
• Those which can't reach adequate speeds could be binned for a PS4Pro Slim.

Manufacturing would improve over the years, and the PS4Pro Slim chips could be phased out, but it's at least a means of selling otherwise junk chips in the first year or two.

Ton of leaps of logic here.

I think it’s mostly likely that the SoC is located beneath the body of the V, with the finstocks placed in the wings of the V so as to maximize surface area for airflow.

 

[Nisaaru]

Obviously wont, looks ugly as sin. PS4 dev kits where big as well so it might be a norm.

To me it makes no sense to design a custom devkit case like this one if that's not an intended form factor for the finished product. And yes it looks ugly as sin which should make people really nervous

 

[Xbat]

It tells me they are trying something different with the cooling or the dev kit has to run at a super high clock because the consoles are going to be on a better process node or the architecture of Navi 2 is more efficient.

Or maybe it's a marketing ploy to get people talking.