Re: ...
Deadmeat said:
According to Moore's Law
CELL@Winter 2009 = 1024 GFLOPS
CELL@Summer 2008 = 512 GFLOPS
CELL@Winter 2006 = 256 GFLOPS
CELL@Summer 2005 = 128 GFLOPS
So you get a Max 128 GFLOPS processor in PSX3. I was right......
MS has nothing to fear from PSX3; it just need to watch its cost, make sure components perform as specified, and developers get a good head start.
Deadmeat, stop being a f*ing idiot.
Moore's Law is a rough bound which describes the decrease in transistor size as plotted against time. Thus, we can use some of that math stuff and state that if the size shrinks by a factor 1/
N at
t+1, and we hold the aggregate area constant we can fit
N times more transistors at
t+1 than at
t.
And as for how 1TFlop
can be explained, logically we're lead to conclude that you can hold more logic per static area as time goes on. We can also state that it just might be, maybe, that FLOPS are a nonlinear function of aggregate logic count. Meaning that in designing an IC like the EE at 250nm, there was a necessary and fixed proportion of the the allowable tranistor budget that's devoted to non-FLOPS producing constructs. There needed to be a DMAC, a MIPS core, etc. These were all mandatory and took up a substantial portion of the allowable budget and because of this you got just 8 FPU's per static construct/core.
When you move to 65nm, you get this massive influx in logic potentiality. And due to the massive influx in logic, the fixed functionality remains relatively constant from the EE to the BE and is now but a small faction of the total area, thus allowing the bulk of the new logic to go toward producing your Flops. Thus we now have 32 FPU's (+32 FXUs) per static construct/core. The influx is enough to further add multiple core/PE's and add to this the process technology advancements(sSOI, Low-K, 65nm, etc), logic effeciency and clock speed grains (Even the massive I-32GS clocked at 600MHz @ 180nm) and you get the patent.
Visually this concept looks like (Note: the line sizes aren't absolute, their relative to the total allowable for each process stepping and the lines are relative proportions):
Code:
Emotion Engine (250nm)
Total Logic Budget:
-------------------------------------------------------------------------------------
Logic for fixed functions:
----------------------------------------------
Logic for FPU/FLOPS:
---------------------------------------
BroadbandEngine (65nm)
Total Logic Budget
-------------------------------------------------------------------------------------
Logic for fixed functions:
-----------
Logic for FPU/FLOPS:
--------------------------------------------------------------------------
In conclusion, FLOPS in this case are a nonlinear function of Moore's Law. Goddamnit, now I'm late. See what you're stupidity does.
