Baseless Next Generation Rumors with no Technical Merits [post E3 2019, pre GDC 2020] [XBSX, PS5]

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I think this graph sums up the potential performance prospect of PS5 pretty well. A mid to slightly high-ish range heavily customized card as usual per console business, that out performs a 12.7tf Vega 64 which explains the need for a 12.9tf devkit (possibly OCed Vega 64) to simulate the final performance of a Navi based 7.5-8tf console. 8 TF PS5 is true after folks and we are going to like it aren't we?
relative-performance_3840-2160.png
 
I think this graph sums up the potential performance prospect of PS5 pretty well. A mid to slightly high-ish range heavily customized card as usual per console business, that out performs a 12.7tf Vega 64 which explains the need for a 12.9tf devkit (possibly OCed Vega 64) to simulate the final performance of a Navi based 7.5-8tf console. 8 TF PS5 is true after folks and we are going to like it aren't we?
relative-performance_3840-2160.png
Yes we are!

According to DF, 5700 outperforms Vega64 at 1440p anywhere from 5-20% at 161W. Which is great result if you ask me. It also outperforms 2060 and pretty much matches 2060S.

Difference between 5700 and XT is relatively small I think duo to only difference being TF, not bandwidth and memory.
 
Yup, Vega 64 performance is what I was hoping we'd get, although I was prepared for something in the realm of Vega 56.

Unless Sony/MS really shit the bed again, we should be in for a great generation.
 
I think this graph sums up the potential performance prospect of PS5 pretty well. A mid to slightly high-ish range heavily customized card as usual per console business, that out performs a 12.7tf Vega 64 which explains the need for a 12.9tf devkit (possibly OCed Vega 64) to simulate the final performance of a Navi based 7.5-8tf console. 8 TF PS5 is true after folks and we are going to like it aren't we?
relative-performance_3840-2160.png

PS Warrior: Navi paid owned by Sony. XB2 uses Radeon VII - old tech!
XB Warrior: No. It's Navi. Possibly Navi+

Benchmarks released.....

PS Warrior: It's about the games…. :/
XB Warrior: Maybe XB2 does use Radeon VII tech.... :/
 
I think this graph sums up the potential performance prospect of PS5 pretty well. A mid to slightly high-ish range heavily customized card as usual per console business, that out performs a 12.7tf Vega 64 which explains the need for a 12.9tf devkit (possibly OCed Vega 64) to simulate the final performance of a Navi based 7.5-8tf console. 8 TF PS5 is true after folks and we are going to like it aren't we?
relative-performance_3840-2160.png

Imagine what that graph would look like with current base PS4, and Pro, to compare Navi+Zen2 with.... that’s the real eye opener here!
Maybe not exactly that graph as it’s native 4K, but you get my point!
 
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Man we're gonna need a new multiplier now after seeing the benchmarks, it seems 1.5-1.6x should be applied seeing how a 8tf RDNA gpu is at least equaling and beating a 12.6tf GCN gpu.
Please don’t do it this way. It’s much too confusing.
FLOP is a FLOP. You can get more saturation or less bottlenecks but it can’t process more than it’s possible floating point operations per second.

Using multipliers is perhaps the most confusing way to do this as there are tons of reasons or benchmarks that will limit cards. Imagine a specific benchmark where if you didn’t have L1 or L2 cache setup a certain way you have immediate 50% loss in performance because the benchmark specifically relies on that and your hardware is using 2-3X more cycles just to get the data into compute.

A 14 wheeler truck has 700HP+ but will lose against a 20HP go kart in benchmarks that favour the go kart. Cards are designed a certain way; software another; benchmarks yet again another way. Something as simple as a benchmark favours nvidia architecture in thy way they do one thing differently. And then with Navi they Make the change to that one thing and all of a sudden performance!
 
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I've not been following any 'technical discussion' in this nonsense thread but from a physicality POV you do not want SRAM anywhere near the a high bandwidth solid state I/O controller given SRAM is particular sensitive to signal noise. We've learnt this the expensive way. :(
It's what Sony claimed would be used in the patent. The main point of that claim that the translation table (and perhaps some data in-flight) is on-die, obviating the need for a large external memory pool and the lower bandwidth of its interface. Even if SRAM proves more sensitive, if it's on-die I don't know what other equivalent options would be available at this point besides SRAM.

Only if the patent states the need for SRAM, like a method and apparatus for accelerating a SRAM cache, would it not be replaceable via DRAM (assuming DRAM can be fast enough).
I would suspect it's difficult to have anything besides an SRAM buffer, if it's on-die. eDRAM doesn't have a source at a modern node, and other options often have specific nodes or have limitations in terms of endurance, capacity, or performance.
The specifics of the storage cells may be interchangeable, but the overall scheme is very concerned with removing the need for external memory chips for the flash controller. It goes to significant effort to contort the flash addressing scheme and translation table handling to shrink the table enough to fit on the die of a flash controller chip.
In the context of the rumor about a devkit with DRAM chips for the SSD and a standard flash controller that uses DDR for its translation tables, it's not evidence for the one element patent that can be visible externally.

I'm largely disregarding this thread and was only intrigued to see what lured 3dilettante here. The specific application favours SRAM (for speed) and SRAM wants to be far from the controller. That's my two pennies' worth.
Random thread perusal, and this patent had come up in other threads before. It's interesting to me in the context of the rumor about a devkit in that it's not often that an architectural element like block addressing and file system can have (or not have) externally visible consequences on a PCB.
 
Please don’t do it this way. It’s much too confusing.
FLOP is a FLOP. You can get more saturation or less bottlenecks but it can’t process more than it’s possible floating point operations per second.

Using multipliers is perhaps the most confusing way to do this as there are tons of reasons or benchmarks that will limit cards. Imagine a specific benchmark where if you didn’t have L1 or L2 cache setup a certain way you have immediate 50% loss in performance because the benchmark specifically relies on that and your hardware is using 2-3X more cycles just to get the data into compute.

A 14 wheeler truck has 700HP+ but will lose against a 20HP go kart in benchmarks that favour the go kart. Cards are designed a certain way; software another; benchmarks yet again another way. Something as simple as a benchmark favours nvidia architecture in thy way they do one thing differently. And then with Navi they Make the change to that one thing and all of a sudden performance!
This is true and all especially with Nvidia tossed into the equation, I still think it's somewhat reasonable to apply it just for Vega vs Navi comparison seeing how the latter is consistently equaling and out performing the former despite a Tflops deficit. Yes, we're only looking at current gen games here, who knows how the next gen game design could shift the % a bit, but I get a feeling they'll be designed with Navi in mind anyway knowing the consoles will be using those and they dictate the vast majority of the industry anyhow.
 
I think this graph sums up the potential performance prospect of PS5 pretty well. A mid to slightly high-ish range heavily customized card as usual per console business, that out performs a 12.7tf Vega 64 which explains the need for a 12.9tf devkit (possibly OCed Vega 64) to simulate the final performance of a Navi based 7.5-8tf console. 8 TF PS5 is true after folks and we are going to like it aren't we?

8 Tflops is a pretty low Number to Start in the end of 2020 , so definitive not a full Step. In this Point I 'm wondering about Sonys new Statement that they targeting the Core Market and that the Ps5 is a "niche Product". Because 8 Tflops( dosent matter if its more effiecient than Vega) is in 2020 already a Mainstream GPU powerwise , you cannot called such Console as a niche Product , or the SSD is the more expensive Part. "Niche" from my Understanding would be a very expensive Console in a price Range of 600-800 Euro.
 
8 Tflops is a pretty low Number to Start in the end of 2020 , so definitive not a full Step. In this Point I 'm wondering about Sonys new Statement that they targeting the Core Market and that the Ps5 is a "niche Product". Because 8 Tflops( dosent matter if its more effiecient than Vega) is in 2020 already a Mainstream GPU powerwise , you cannot called such Console as a niche Product , or the SSD is the more expensive Part. "Niche" from my Understanding would be a very expensive Console in a price Range of 600-800 Euro.
I also think the word Niche is only in relative term, compared to previous gen consoles it indeed is, but not so much compared to gpus from 2020. Unless Sony surprise the shit out of us by introducing a $599 console again with 10TF+ Navi, 16GB HBM all cooled by a monster vapor chamber, the chance of that happening is less than 5% the way I see it.
 
Patent law was developed for use by the layman. You don't need a lawyer, nor to be a lawyer, to create a patent, although writing one that adequately protects your IP without knowing how patent lawyers can look for loopholes is risky.

Over 500 years ago when the first concept of patents were established, yes. Not any longer.

It is how I say (unless there's been a major overhaul in the last 10 years I don't know about) - a patent description is not in any way binding.

None of it is binding, patent legislation is a technical branch of contract law overseen by civil courts in most countries. While the State may provide the framework and process for assessments (applications) and record keeping (patents being issued) it does not enforce that. That's down to individuals in court, hence the specialism of patent lawyers.

Good luck to you if you want to everything yourself but if the purpose of obtaining a patent is protection, with no experience of practising in patent law, nor knowledge of key patent decisions in the courts, I wouldn't rate your chances of writing a good patent application.

It's what Sony claimed would be used in the patent.

I must have missed the reference to SRAM in the patent, I only saw conjecture of the possible of use of DRAM in system memory, where the patent itself questioned what impact this arrangement would have on efficiency.
 
I must have missed the reference to SRAM in the patent, I only saw conjecture of the possible of use of DRAM in system memory, where the patent itself questioned what impact this arrangement would have on efficiency.

Referring to the link given earlier:
http://www.freepatentsonline.com/y2017/0097897.html

If the address conversion table to be referred to is stored in the flash memory 20, the flash memory 20 is accessed at a higher frequency for address conversion, thus resulting in lower processing throughput and increased latency. Efficiency can be enhanced by caching a large part of the address conversion table, for example, to an external DRAM. The larger the capacity of the flash memory 20, the larger the capacity of a necessary DRAM. Further, DRAM data transfer rate has become dominant, making it difficult to anticipate sufficient improvement in throughput and latency after all.

In the present embodiment, therefore, the address conversion table size is minimized by increasing the data processing unit in response to a write request, i.e., granularity level, at least for part of data. Assuming, for example, that the write granularity level is 128 MiB and that data of each entry in the address conversion table is 4 bytes in size as described above, the data size of the address conversion table as a whole is a ½25th fold of the capacity of the flash memory 20. For example, a 32-KiB (32λ210 bytes) address conversion table can express 1 TiB (240 bytes) of area.

Thus, storing a sufficiently small-sized address conversion table in the SRAM 24 of the flash controller 18 makes it possible to convert addresses without the mediation of an external DRAM. Making the write granularity coarser is particularly effective, for example, for game programs that are loaded from an optical disc or network, stored in the flash memory 20, and only repeatedly referred to. This means that because stored data is not rewritten, it is not necessary to reserve a new area for storing rewritten data in that unit.

And then later:

In the present embodiment described above, the granularity level of access to write to the flash memory is larger than the related art write granularity level such as that on a page-by-page basis. This brings the entire address conversion table down to a size that can be stored in a built-in SRAM, thus making it unnecessary to repeatedly access the flash memory for address conversion. Further, even if the capacity of the flash memory is larger, it is no longer necessary to provide a large-capacity external DRAM so as to cache the address conversion table. As a result, it is possible to not only prevent increased latency and lower throughput resulting from access to the flash memory and the external DRAM but also provide reduced manufacturing costs and chip area.
 
I wouldn't be surprised if this is an AMD spec'd Gaming/Workstation laptop competing against Nvidia's spec'd (Turing mobile architecture) laptops that contain either the RTX 4000 or RTX 5000 GPUs that have 16GB of GDDR6 on a 256-bit bus. I know Asus is refreshing their AMD ROG line soon with the new Navi / Ryzen architectures, as well as their competitors.

Anyhow, those boost-clocks for console gaming is a no-go on so many levels, especially when framerate prediction (stability) and input latency would be drastically affected by that gulf between the normal clocks and boost-clocks. Console gaming aims for a more uniformed approach (hardware/software/performance) towards the user's experience within that console userbase and ecosystem.
 
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Turing 5000 in those laptop is 16GB for GPU, its not system memory.

I know that. I'm just stating the possibilities that this APU configuration could house such a configuration towards the GPU component, not the general / OS memory configuration. There could be a possibility of 8-16GB of DDR4 for such needs. A split memory configuration which PCs and laptops are already accustomed to. The APU package (for this particular laptop) could just be a way on cutting down on thermals, footprint size and BoM cost.
 
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