Next Generation Hardware Speculation with a Technical Spin [2018]

[Mihailjones]

you realize that MS had the same thing at launch through Kinect voice controls ? You wouldn't even need to go into a menu with a long press. Just say xbox record that , xbox share that. Now that's quite the innovation and now amazon and google sell tens of millions if not hundreds of millions of voice assistant products.

Anyway I doubt this conversation will continue any further. My point still stands that while Kinect did not do well on the xbox one to say its feature set hasn't been adopted and beomce industry standards is a big ridiculous

I haven't moved anything. The point of something becoming an industry standard vs another thing stands.

That is not innovative, that is just stupid gimmick.

Maybe it works for native english talkers, but not for others, whom cant pronounce things like natives

And it get really old really fast to repeat those commands, while pressing a button is silent and fast.

Imagine someone playing at night with headphones to be silent, and then yelling commands to the mic

 

[eastmen]

That is not innovative, that is just stupid gimmick.

Maybe it works for native english talkers, but not for others, whom cant pronounce things like natives

And it get really old really fast to repeat those commands, while pressing a button is silent and fast.

Imagine someone playing at night with headphones to be silent, and then yelling commands to the mic

if your playing silent with headphones why would you need to yell a command ?

I rather speak what I want the system to do instead of breaking off from the game with a series of button presses. Esp true in multiplayer gaming

 

[Tkumpathenurpahl]

Both are useful implementations of the same feature. The best option IMO is to have a button and Akexa level voice controls.

Better yet, let's not argue about which is better, when we've identified that the feature we all really want is "convenient screenshot and video capture capability."

 

[Tkumpathenurpahl]

256 bit may not be enough. Is it practical to move CPUs off die to save 70 mm^2?

Wouldn't it be more a matter of taking advantage of CPU chiplet binning rather than just saving die space? And if an extra 70mm^2 of GPU replaced the area left by the CPU, I'd be a happy camper.

Also, could it potentially save on some degree of customisation costs by way of using off the shelf Zen 2 chiplets, as well as grant them easy transitions to future nodes?

 

[anexanhume]

Wouldn't it be more a matter of taking advantage of CPU chiplet binning rather than just saving die space? And if an extra 70mm^2 of GPU replaced the area left by the CPU, I'd be a happy camper.

Also, could it potentially save on some degree of customisation costs by way of using off the shelf Zen 2 chiplets, as well as grant them easy transitions to future nodes?

Perhaps, but I’m going to guess they’ll want 8 full cores with good performance profiles (ideal mobile chips). They won’t be taking the scraps from the epyc or desktop lines.

 

[mrcorbo]

Perhaps, but I’m going to guess they’ll want 8 full cores with good performance profiles (ideal mobile chips). They won’t be taking the scraps from the epyc or desktop lines.

There's also the matter, though, of the best process for manufacturing CPUs and GPUs being different. The Gamer's Nexus Youtube channel had a sit-down chat with David Kanter and Steve Burke from Intel's architecture event and they go into 2.5d and 3d manufatcuring techniques. Making a monolithic die inherently means that you will not be using the optimal process for one or the other component.

 

[anexanhume]

There's also the matter, though, of the best process for manufacturing CPUs and GPUs being different. The Gamer's Nexus Youtube channel had a sit-down chat with David Kanter and Steve Burke from Intel's architecture event and they go into 2.5d and 3d manufatcuring techniques. Making a monolithic die inherently means that you will not be using the optimal process for one or the other component.

I doubt it will ever be the case where the best process for a console GPU wouldn’t also be the best process for its CPU given they’re not operating in the mobile/SoC dissipation range. You’d choose another process because it’s cheaper for a given performance, whether that be because of lack of scaling of die area or transistor dissipation for a given workload, like an IO die.

______________________________

So this seems pretty significant. Sony has applied for a patent on a heatsink that sits on the opposite side of the PWB of the APU has thru-hole thermal conduits that touch the bottom side of the package (the area is voided by virtue of a package with fan-out that avoids the center of the device). It also appears to depict (amongst other things), stacked die within the package (5c, 5d) and another heatsink or other assembly on the top of the package (9).


This is pretty exciting.

https://imgur.com/a/lfPx7MI

The following two patents are also cool. Cloud-side emulation with local boost mode, and Just-in-time dynamic reconciliation of code.


http://www.freepatentsonline.com/y2018/0341531.html

http://www.freepatentsonline.com/y2018/0357149.html

 

[bgroovy]

I rather speak what I want the system to do instead of breaking off from the game with a series of button presses. Esp true in multiplayer gaming

Yeah, but if you have a conveniently located share button it's an instant, single press. The delay for voice processing alone makes it hard to get in the moment shots.

 

[Shifty Geezer]

Let's end that conversation. Voice controls and button presses have their pros and cons. Ideally, we'll have both and keep everyone happy.

 

[MrFox]

I doubt it will ever be the case where the best process for a console GPU wouldn’t also be the best process for its CPU given they’re not operating in the mobile/SoC dissipation range. You’d choose another process because it’s cheaper for a given performance, whether that be because of lack of scaling of die area or transistor dissipation for a given workload, like an IO die.

______________________________

So this seems pretty significant. Sony has applied for a patent on a heatsink that sits on the opposite side of the PWB of the APU has thru-hole thermal conduits that touch the bottom side of the package (the area is voided by virtue of a package with fan-out that avoids the center of the device). It also appears to depict (amongst other things), stacked die within the package (5c, 5d) and another heatsink or other assembly on the top of the package (9).


This is pretty exciting.

https://imgur.com/a/lfPx7MI

The following two patents are also cool. Cloud-side emulation with local boost mode, and Just-in-time dynamic reconciliation of code.


http://www.freepatentsonline.com/y2018/0341531.html

http://www.freepatentsonline.com/y2018/0357149.html

That heatsink is solving the stacked memory issue which prevented it to appear on any high power console or gpus. That's one reason why the Vita had it but not the ps4.

But even for single die, it doubles the energy density possible. Twice the actual contact area.

The fanout is also very simple since there are no massive memoey busses to get through, just power and a few pcie lanes. No need for expensive silicon here.

HBM3 will be able to stack on chip, I think that's the first one. Should be very low power.

 

[anexanhume]

That heatsink is solving the stacked memory issue which prevented it to appear on any high power console or gpus. That's one reason why the Vita had it but not the ps4.

But even for single die, it doubles the energy density possible. Twice the actual contact area.

The fanout is also very simple since there are no massive memoey busses to get through, just power and a few pcie lanes. No need for expensive silicon here.

HBM3 will be able to stack on chip, I think that's the first one. Should be very low power.

Not sure that I follow. Nvidia and AMD already put HBM2 stacks on some cards in 2.5D configurations and manage to cool massive TDP GPUs in the process.

Total surface area doesn’t double because you can’t contact both sides of the die. Effective surface can increase since the die and memory get separate heatsinks, but why give the die the more compromised heat path through the PWB?

What are you saving by putting the memory on the opposing side vs the same side? The total IO doesn’t change, so if you needed an interposer vs. HDI substrate, that need will still exist. If you are hoping to put GDDR6 chips on there to relax IO count and get away with a traditional package and no interposer, I think the package size becomes a non-starter even with just 8 chips.

 

[MrFox]

There is a power difference between putting it side by side through an interposer (hbm, hbm2) versus having it directly on top like wideIO and what they plan for hbm3. The power required for the interface should be much lower.

Hot SoC cannot put the memory on top, it doesn't conduct well through.

A completely different possibility is not stacking the memory and getting twice the surface to cool a single die.

 

[anexanhume]

There is a power difference between putting it side by side through an interposer (hbm, hbm2) versus having it directly on top like wideIO and what they plan for hbm3. The power required for the interface should be much lower.

Hot SoC cannot put the memory on top, it doesn't conduct well through.

A completely different possibility is not stacking the memory and getting twice the surface to cool a single die.

The image doesn’t depict a stacked configuration as you suggest. IMO, it clearly shows a die mounted “upside down” on the bottom of the package in a void in the BGA. Then, there’s a TIM and some sort of metal plate, and the plate attaches to the heat sink on the opposing side of the PWB with metal posts extending through the PWB like through-hole mount parts of yore. I’m sure the metal post me will dump a little thermal energy into the PWB’s ground planes, at least.

I don’t understand how you’re formulating that you’ll have twice the area to cool a single die. The die has to fanout somewhere, and the only heat dissipation you’re going to get there is through vias into substrate bulk, which won’t be great.

 

[MrFox]

5c and 5d are not stacked dies?

 

[anexanhume]

5c and 5d are not stacked dies?

5a is not stacked. It’s the one mounted on the underside. 5c and 5d are harder to tell. They look to be package embedded, which really hasn’t been done for active silicon yet. That’s why I’m hesistant to draw too many conclusions about the stacking depicted here.

 

[AlNom]

That's certainly beyond 3d.

 

[MrFox]

5a is not stacked. It’s the one mounted on the underside. 5c and 5d are harder to tell. They look to be package embedded, which really hasn’t been done for active silicon yet. That’s why I’m hesistant to draw too many conclusions about the stacking depicted here.

I wonder if the substrate itself can conduct enough heat for that side to have the memory, and the SoC side would be the more massive heatsink. It's certainly better than having to go through the BGA and the PCB.

Yeah I'm not sure anymore what we're seeing.

The heat path 11 kind of looks like ordinary filled via stitching, which is not exactly a new thing in heat management. It's also limited in performance and usually just for maybe 10 watts, not nearly good enough for 100+ watts.

Maybe this is for a portable device thickness.

 

[anexanhume]

I wonder if the substrate itself can conduct enough heat for that side to have the memory, and the SoC side would be the more massive heatsink. It's certainly better than having to go through the BGA and the PCB.

Yeah I'm not sure anymore what we're seeing.

The substrate is going to be a poor thermal path unfortunately.

https://en.m.wikipedia.org/wiki/Wiedemann–Franz_law

The heat path 11 kind of looks like ordinary filled via stitching, which is not exactly a new thing in heat management. It's also limited in performance and usually just for maybe 10 watts, not nearly good enough for 100+ watts.

Maybe this is for a portable device thickness.

The language specifically says “through-hole”, which would typically refer to solid components placed through the board rather than a filled via hole. I would think you’d be worried about solder coverage and cracking in a high stress area like this (both via heat expansion and contraction and mechanical via whatever retention mechanism this would need, which is not depicted.)

A single assembly (imagine a bed of nails type metal construction) would like be a better overall heat path if the design supported it.

A lot of the unknowns are why I think you’d want to test it in a PS4 super slim first, which I think this patent could actually be for. Imagine a 7nm APU on the underside and 4 GDDR6 chips up top, similar to the PS3 Super Slim’s transition from GDDR3 to GDDR5 and halving of the bus width. You don’t want another Xbox 360 RROD issue on your hands.

 

[Deleted member 13524]

5c and 5d are not stacked dies?

A reverse image search only leads to @anexanhume 's post so I can't see the rest of the description. Maybe he could point out the source directly?


However, 5d and 5c do seem like stacked ICs, meaning it could be a solution to help dissipate the heat in a true 3D stacking that foregoes the interposer.
They could be getting one or more HBM stacks mounted upside-down (5d), underneath a larger SoC (5c) both of them connected using TSV. The under-PCB heatsink could help prevent the HBM stacks from overheating, and then a large heatsink could be put on top of 5c (SoC).

It could also be used to create a heat dissipation system for a device that requires very low z-height (e.g. smartphone, tablet, PS4 Go..).



2019 seems to be the starting year of 3D stacking for many, so heat dissipation for such a solution is obviously a growing concern.

 

[anexanhume]

A reverse image search only leads to @anexanhume 's post so I can't see the rest of the description. Maybe he could point out the source directly?


However, 5d and 5c do seem like stacked ICs, meaning it could be a solution to help dissipate the heat in a true 3D stacking that foregoes the interposer.
They could be getting one or more HBM stacks mounted upside-down (5d), underneath a larger SoC (5c) both of them connected using TSV. The under-PCB heatsink could help prevent the HBM stacks from overheating, and then a large heatsink could be put on top of 5c (SoC).

It could also be used to create a heat dissipation system for a device that requires very low z-height (e.g. smartphone, tablet, PS4 Go..).



2019 seems to be the starting year of 3D stacking for many, so heat dissipation for such a solution is obviously a growing concern.

It’s a patent application, so the single image is the only thing disclosed.

http://www.freepatentsonline.com/WO2018216627A1.pdf

In the image disclosed, 5c and 5d appear within the package assembly, rather than on top of it. 5a is the only device depicted on an exterior surface of the package. (9) is depicted floating, apparently. Having access to the full patent would help tremendously. I’m not holding it back