Next Generation Hardware Speculation with a Technical Spin [2018]

[Jay]

So it won't have any impact on backwards compatibility?

Was talking strictly about the marketing, and why the core count wouldn't matter in that regards.

maybe a zen based 4c8t would be fast enough that any potential issues with bc would be mitigated.
bit like the lack of esram in the 1X.
but this wasn't really my point

 

[itsmydamnation]

Was talking strictly about the marketing, and why the core count wouldn't matter in that regards.

maybe a zen based 4c8t would be fast enough that any potential issues with bc would be mitigated.
bit like the lack of esram in the 1X.
but this wasn't really my point

Just go look at the Subor Z Plus, its frame rates are in the same range / higher then PS4pro (BF1) and that's with the overhead of windows and DX11 with higher settings.

This whole Zen lite stuff is almost as stupid as the whole EPYC 2 uncore die logic. So Sony is going to pay AMD hundreds of millions of dollars (lets call it 100*) to design/validate/produce a core over 2-4 years that's close to Zen2 but "lite". How much is that lite going to save you over 8 cores? a Zen 1 core is 7mm (including L1, L2) , TMSC 7nm is expected to be around 4x the density of 16nm. looks like AMD are using HPC node so it will be less and logic wont scale like that but their is still a shed load of sram and there are rumors of 256bit paths so lets call it 3.5mm a Core. So your Cores + L1 + L2 are costing you 28mm sq ..........

Even if you halved the core size your saving like 14mm
There are like 70,000 mm sq in a 300mm circle
Lets say a 7nm wafer costs 14k
Thats means each mm sq costs 20c, so your saving $2.80 a die in manufacturing costs,
So what 35 million consoles needing to be sold just to break even for less performance........
But wafer costs wont stay that high and might not even be that high when consoles are ramping for production let alone 3,4,5 years in ( i expect a long time until a 5nm refresh)

Seriously put the crack pipes down!

*AMD said Zen was 400million over 4 years, 7nm will drive costs higher as well

 

[Jay]

Just go look at the Subor Z Plus, its frame rates are in the same range / higher then PS4pro (BF1) and that's with the overhead of windows and DX11 with higher settings.

This whole Zen lite stuff is almost as stupid as the whole EPYC 2 uncore die logic. So Sony is going to pay AMD hundreds of millions of dollars (lets call it 100*) to design/validate/produce a core over 2-4 years that's close to Zen2 but "lite". How much is that lite going to save you over 8 cores? a Zen 1 core is 7mm (including L1, L2) , TMSC 7nm is expected to be around 4x the density of 16nm. looks like AMD are using HPC node so it will be less and logic wont scale like that but their is still a shed load of sram and there are rumors of 256bit paths so lets call it 3.5mm a Core. So your Cores + L1 + L2 are costing you 28mm sq ..........

Even if you halved the core size your saving like 14mm
There are like 70,000 mm sq in a 300mm circle
Lets say a 7nm wafer costs 14k
Thats means each mm sq costs 20c, so your saving $2.80 a die in manufacturing costs,
So what 35 million consoles needing to be sold just to break even for less performance........
But wafer costs wont stay that high and might not even be that high when consoles are ramping for production let alone 3,4,5 years in ( i expect a long time until a 5nm refresh)

Seriously put the crack pipes down!

*AMD said Zen was 400million over 4 years, 7nm will drive costs higher as well

I'm not sure if you was on the pipe when you wrote this or not, or quoted me by mistake?

i was very clear in what i was referencing.
or are you saying that a 4c8t zen definately wouldn't be enough to handle bc(backwards compatibility)?
or that it would be so bad due to marketing?

I hopefully was clear that i wasn't saying if it's a good idea, powerful enough for next gen games etc as that wasn't what was being discussed from what i saw. So i specifically threw in my 2 cents in regards to marketing (then bc)


out of curiosity the example you used, was it using things like primitive shaders?

 

[VitaminB6]

With this tread being called "Next Generation Hardware Speculation: Dreams, Wishes, Cluelessness and a Dash of Reality [2018]" someone has to be the clueless one (that's me). I'm OK if others want to bring a dash of reality though. It's going to be Zen Lite for sure...

 

[Jay]

With this tread being called "Next Generation Hardware Speculation: Dreams, Wishes, Cluelessness and a Dash of Reality [2018]" someone has to be the clueless one (that's me). I'm OK if others want to bring a dash of reality though. It's going to be Zen Lite for sure...

It was bad quoting, in conjunction to pipe comment, then talking about nothing that was quoted that made me raise eyebrow haha

 

[Megadrive1988]

My bet is PS5 & Xbox Scarlett will use 8 core / 16 thread ZEN 2 - with reasonable clocks (i.e. not 3.5 - 4+ GHz like you might see with Ryzen 3000 desktop processors) but maybe 3.0 to 3.2 GHz.

 

[shiznit]

With temporal reconstruction techniques (now inference-based options as well) and dynamic resolutions becoming mainstream, I'd much rather trade some GPU die area for 8 CPU cores. We'll likely be stuck on 7nm for a long time and I'd love to see what first party studios can do with all that CPU power.

 

[function]

My bet is PS5 & Xbox Scarlett will use 8 core / 16 thread ZEN 2 - with reasonable clocks (i.e. not 3.5 - 4+ GHz like you might see with Ryzen 3000 desktop processors) but maybe 3.0 to 3.2 GHz.

Somewhere roughly around .7 (give or take) of max shipped clocks for the architecture on a given process seems to be where consoles usually go. I image that's were power curves and possibly yields start to move into unfavourable territory.

If 8 core Zen 2 on 7nm hits 4.2 ~4.5 gHz (none turbo) for high end SKUs I think we'll see something in the 3 ~ 3.3 range for 8 core on console.

And that power will be un-necessary for the first couple of years for multiplatform games, as PS4 capable games, and games able to run comfortably on mainstream and laptop i5s, will be in the majority. I hope that mean's we'll see 60+ fps optional modes from day one on PS5/X4.

 

[VitaminB6]

Somewhere roughly around .7 (give or take) of max shipped clocks for the architecture on a given process seems to be where consoles usually go. I image that's were power curves and possibly yields start to move into unfavourable territory.

If 8 core Zen 2 on 7nm hits 4.2 ~4.5 gHz (none turbo) for high end SKUs I think we'll see something in the 3 ~ 3.3 range for 8 core on console.

And that power will be un-necessary for the first couple of years for multiplatform games, as PS4 capable games, and games able to run comfortably on mainstream and laptop i5s, will be in the majority. I hope that mean's we'll see 60+ fps optional modes from day one on PS5/X4.

If we assume it's a Zen with 8 physical cores. Could anyone guestimate what we'd be looking at for the remaining die area, and what that would give for a CU count if we assume Vega? If the chip is somewhere in the 360mm2 range. Also do you think the die size will be in the same range as last gen?

 

[function]

If we assume it's a Zen with 8 physical cores. Could anyone guestimate what we'd be looking at for the remaining die area, and what that would give for a CU count if we assume Vega? If the chip is somewhere in the 360mm2 range. Also do you think the die size will be in the same range as last gen?

Don't know about die areas sorry. There are some pretty educated guesses about 7nm Zen cores, but then you have to throw in L3 size, cost of whatever type of fabric connects them, cost of ... whatever that extra stuff in the L3 reduced Zen APUs is .... I don't really know beyond the guesses anyone else has put forward. Sorry to be a killjoy!

CU count is difficult as we don't yet know if Navi can scale beyond 64, and Navi is likely to be the base for next gen systems. CU count will also be affected by die area, and that will be affected by yields and the number of redundant units you can afford.

My own, incredibly simplistic way of looking at this is that for 7nm to be ready for the mainstream the defect rate will need to be somewhere kinda-roughly where it was in 2013. And with cost per transistor being about the same or a little higher by late 2019 / 2020 we're probably looking at the same kind of upper bound for chip area, which is to say <400 mm^2.

7nm Vega will and Zen 2 should give us lots of info to pour over before summer 2019!

 

[anexanhume]

If we assume it's a Zen with 8 physical cores. Could anyone guestimate what we'd be looking at for the remaining die area, and what that would give for a CU count if we assume Vega? If the chip is somewhere in the 360mm2 range. Also do you think the die size will be in the same range as last gen?

Vega 55/64 is a 484 mm^2 die for reference. Zeppelin (8 core Zen) is 213 mm^2. Applying TSMC’s 70% scaling factor from 14/16 to 7, you get 203 mm^2. Keep in mind we’re double counting at least memory controllers there.

PS4/XB1/PS4P/XB1X all live in the 340-360mm^2 range, so I think we can reasonably expect some CPU core growth and CU size and count growth over 64 Vega CUs and still potentially fit in that.

 

[itsmydamnation]

Vega 55/64 is a 484 mm^2 die for reference. Zeppelin (8 core Zen) is 213 mm^2. Applying TSMC’s 70% scaling factor from 14/16 to 7, you get 203 mm^2. Keep in mind we’re double counting at least memory controllers there.

PS4/XB1/PS4P/XB1X all live in the 340-360mm^2 range, so I think we can reasonably expect some CPU core growth and CU size and count growth over 64 Vega CUs and still potentially fit in that.

I think your a bit optimistic

I would assume the consoles are using 7 HPC like Rome/Vega 20 , so scaling will be worse then standard 7nm, clocks should be higher, but on the upside i think there is a lot more then just memory controllers that can be tossed from the CPU SOC side, the Subor Z+ is <400mm sq on 14nm , we dont know how many CU's it has in total (28?). A straight doubling of that would give a 512bit bus 8 cores and 56? CU's.

If you kept performance per unit constant to 14nm, a 60% scale factor* , 65% power reduction, 8 cores , 56CU/ 8TF my guess would be ~320 mm sq at 130 watts. So 64 CU in 350mm doesn't seem extreme, removal of 128/256bit of memory controller would also help, if HPC doesn't cost as much as i have factored in that would also help. Also people are guessing that the Subor is made at GF and i think N16FF+ is better all round process so my extrapolation are probably slightly pessimistic.

So i think 8 cores @ 3.3-3.5 ghz, 64 CU's @ 1.5ghz in 350mm^2 @ 150 ish watts is what we will get.

cant find any detail on the real world size cost of moving from 6 tracks to 7.5 for HPC
https://www.semiwiki.com/forum/content/7443-top-10-highlights-tsmc-2018-technology-symposium.html

 

[anexanhume]

I think your a bit optimistic

I would assume the consoles are using 7 HPC like Rome/Vega 20 , so scaling will be worse then standard 7nm, clocks should be higher, but on the upside i think there is a lot more then just memory controllers that can be tossed from the CPU SOC side, the Subor Z+ is <400mm sq on 14nm , we dont know how many CU's it has in total (28?). A straight doubling of that would give a 512bit bus 8 cores and 56? CU's.

If you kept performance per unit constant to 14nm, a 60% scale factor* , 65% power reduction, 8 cores , 56CU/ 8TF my guess would be ~320 mm sq at 130 watts. So 64 CU in 350mm doesn't seem extreme, removal of 128/256bit of memory controller would also help, if HPC doesn't cost as much as i have factored in that would also help. Also people are guessing that the Subor is made at GF and i think N16FF+ is better all round process so my extrapolation are probably slightly pessimistic.

So i think 8 cores @ 3.3-3.5 ghz, 64 CU's @ 1.5ghz in 350mm^2 @ 150 ish watts is what we will get.

cant find any detail on the real world size cost of moving from 6 tracks to 7.5 for HPC
https://www.semiwiki.com/forum/content/7443-top-10-highlights-tsmc-2018-technology-symposium.html

It may be too optimistic, even with the redundancy contingencies. Let’s see what 7nm Vega looks like.

 

[Kaotik]

It may be too optimistic, even with the redundancy contingencies. Let’s see what 7nm Vega looks like.

It looks like this:

 

[bitsandbytes]

Vega 55/64 is a 484 mm^2 die for reference. Zeppelin (8 core Zen) is 213 mm^2. Applying TSMC’s 70% scaling factor from 14/16 to 7, you get 203 mm^2. Keep in mind we’re double counting at least memory controllers there.

PS4/XB1/PS4P/XB1X all live in the 340-360mm^2 range, so I think we can reasonably expect some CPU core growth and CU size and count growth over 64 Vega CUs and still potentially fit in that.

Maybe you can help me understand the scaling figures here anexanhume. They always get me confused.

As I understand it, it is like this:

OG 28nm PS4 is 348mm^2 and 16nm Slim is ~235-240mm^2 or a ~30-35% scale?
Vega 14nm is 484mm^2 and my guess for the picture of 7nm Vega Kaotik posted above is ~330-340mm^2 or again a ~30-35% scale?

Like I say I might well be confused but it seems to my mind a 30-35% scale is more realistic going from 14/16nm to 7nm for similar complexity?

 

[megre]

This is my first post and probably my only post. I only registered to satisfy my curiosity with one question. I know many of you here are very well-versed with how things work on these machines.

I heard from rumors that Sony or MS may be using seperate cpu and gpu. I've also read that an 8 core/16 threads zen2 cpu is less than 200mm in die size, probably even less than 100mm? So my question is, is it possible to pair up an APU + GPU?

APU (200mm+/-) + GPU (200mm+/-)

It it's possible, do you think it'll be cheaper than a bigger 300mm+ die APU? And do you think with this set-up, they can achieve 20 teraflops of over-all throughput? Thanks in advance. I'm already excited for next-gen, I hope it comes out next year.

 

[itsmydamnation]

Maybe you can help me understand the scaling figures here anexanhume. They always get me confused.

As I understand it, it is like this:

OG 28nm PS4 is 348mm^2 and 16nm Slim is ~235-240mm^2 or a ~30-35% scale?
Vega 14nm is 484mm^2 and my guess for the picture of 7nm Vega Kaotik posted above is ~330-340mm^2 or again a ~30-35% scale?

Like I say I might well be confused but it seems to my mind a 30-35% scale is more realistic going from 14/16nm to 7nm for similar complexity?

Vega 20 is not Vega 10,

of the things we know,
1. it has 2 extra memory channels
2. it has much higher DP rate (should be 1/2)
3. it has AI ops (i assume int4, FP8, non IEEE sig/exponent bits)

 

[Kaotik]

This is my first post and probably my only post. I only registered to satisfy my curiosity with one question. I know many of you here are very well-versed with how things work on these machines.

I heard from rumors that Sony or MS may be using seperate cpu and gpu. I've also read that an 8 core/16 threads zen2 cpu is less than 200mm in die size, probably even less than 100mm? So my question is, is it possible to pair up an APU + GPU?

APU (200mm+/-) + GPU (200mm+/-)

It it's possible, do you think it'll be cheaper than a bigger 300mm+ die APU? And do you think with this set-up, they can achieve 20 teraflops of over-all throughput? Thanks in advance. I'm already excited for next-gen, I hope it comes out next year.

It's possible (it's been done forever as "hybrid crossfire") but you'd lose some synergies of having the CPU and GPU on same die, unless you build a really expensive and fat cache coherent bus between the two (and even then latencies would be higher)

 

[bitsandbytes]

Vega 20 is not Vega 10,

of the things we know,
1. it has 2 extra memory channels
2. it has much higher DP rate (should be 1/2)
3. it has AI ops (i assume int4, FP8, non IEEE sig/exponent bits)

Right, I get that 7nm Vega is a professional market GPU but does that affect the scaling figures significantly i.e. from ~35% to ~70%?

 

[itsmydamnation]

Right, I get that 7nm Vega is a professional market GPU but does that affect the scaling figures significantly i.e. from ~35% to ~70%?

Put simply Yes, DP multipliers are like 4 times bigger then SP multipilers ( if i remember correctly), memory interfaces aren't insignificant, memory controllers aren't either. I dont know if a PCIe-4 interface takes up more room then a 3?

Also remember that the die is always a little smaller then the package you see, people originally pixel counted 510ish for vega 10, it was 484.

Also also AMD are using 7HPC which has 7.5 tracks not 6 like regular 7nm, scaling wont be to 70% reduction level.