That thing is called Platform Security Processor. It has been a thing for a while, since its first appearance in the Bemma APU. Basically it is trusted root + secure bootchain + crypto engine, and SME/SEV (announced a few months ago as a whitepaper) works on top of it.
That thing is called Platform Security Processor. It has been a thing for a while, since its first appearance in the Bemma APU. Basically it is trusted root + secure bootchain + crypto engine, and SME/SEV (announced a few months ago as a whitepaper) works on top of it.
more benchmarks, Ryzen is coming!!
So happy for AMD. Intel are decreasing prices, plus they are quite worried and doing malpractices to the point that they are sending press releases asking journalists to call them before publishing Ryzen reviews, because of things like that their CPU that costs more than 1000€ lags behind in some things compared to a Ryzen that costs 500€ , both CPUs feature 16 cores and 20MB cache, while the Ryzen has less power consumption.https://translate.google.com/transl...-en-sniper-elite-4-102447/&edit-text=&act=url
If the real benchmarks live up to the hype so far then I've seriously considering getting a 1700 or 1700x. It's been a long time since I've had an AMD CPU but I'll happily go back at those prices.
The clocks and TDP for the 1700 might hint at what a quad-channel product might provide, since AMD may be segmenting partially on memory specs. A product equivalent to two SR die could give ~130W or so, which may explain why there isn't a 140W product yet.
Possibly, a "2700" might bump 2x1700 to be a "2700X" in order to account for overhead, or it might have lower clocks to compensate--perhaps slightly offset by a broader XFR range. Given the cachet such a product could have, AMD might bump the PR number higher.
The gap between the 1700 and 1700X in TDP is a too broad to double the latter without putting in the FX-9590 range.
A fun experiment might be if AMD's solution was flexible enough to mix a 1700X die and a 1700, to slot it somewhere around where the highest TDP Xeons might go. That might be a bit of hassle to tune that kind of product, unless the properties of the two dies were somehow made explicit.
Possibly, a "2700" might bump 2x1700 to be a "2700X" in order to account for overhead, or it might have lower clocks to compensate--perhaps slightly offset by a broader XFR range. Given the cachet such a product could have, AMD might bump the PR number higher.
The gap between the 1700 and 1700X in TDP is a too broad to double the latter without putting in the FX-9590 range.
A fun experiment might be if AMD's solution was flexible enough to mix a 1700X die and a 1700, to slot it somewhere around where the highest TDP Xeons might go. That might be a bit of hassle to tune that kind of product, unless the properties of the two dies were somehow made explicit.
Silent_Buddha
Legend
All this hype kind of makes me glad I haven't upgraded my i5 2500k. I almost pulled the trigger last fall, but I'm glad I didn't now. Well, assuming Ryzen lives up to all the hype generated by these leaks. And even if it doesn't fully, Intel chips have gotten cheaper, so win win.
Regards,
SB
I almost pulled the trigger last fall, but I'm glad I didn't now. Well, assuming Ryzen lives up to all the hype generated by these leaks. And even if it doesn't fully, Intel chips have gotten cheaper, so win win.Regards,
SB
AnandTech has both the highest resolution in Bistrol Ridge/Carrizo and Summit Ridge AFAIK.
AMD has been using home snooping since forever (hmm, K8). So regardless of where a request is originated, it must be forwarded to its home memory controller for handling. "Memory controller" (MCT) in AMD's world is more than just a DDR controller — it is also a coherency manager for the MOESI protocol of its respective physical address space, or "Home Agent" if you prefer Intel's nomenclature. In Istanbul, Magny-Cours and Interlagos, the MCT "stoles" L3 cache to maintain an sparse directory inclusive of all cache lines backed by the node (aka HT Assist).
A directory filtering requests in/out an SMP link just doesn't make sense. If it gonna filter outgoing request, the authority of it lies in its home node unless you wanna synchronise multiple directories across chips. Let alone all the topology and networking concerns. If it gonna filter incoming request, the authority of it lies in the MCT of the same die, or it could be a pass-thru packet to other nodes, so it is practically useless/impossible to implement.
Well, I'd say both, if you expect 16-core Naples to have half I/O of its 32-core brother, i.e. 64 SerDes lanes. The MCM would use the supposedly on-package I/O. This way two chips give 64 lanes in total, and some of them might be capable of carrying GMI, SATA and Ethernet instead of just PCIe.
The chipset should use the x4 block regardless. 32 lanes are sufficient for what Summit Ridge requires (x16 + x4 + x4).
I would be surprised if it is the case. But the alleged HPC APU slide goes against this theory.
Anarchist4000
Veteran
The benefits of the HPC APU seem like they would be well worth it. Not as much for the APU and coprocessor abilities, but the possibility of integrating HBM2 as a cache along with a wide link between processors. A single stack is twice the bandwidth of a 4 channel DDR4 configuration and likely with better timings and energy efficiency. The HBCC with Vega could be a Naples construct that got adopted. There would certainly seem to be some performance benefits of that arrangement.
from that CPUz numbers
wow shows how little CPUs have improved over the last few years, that CPU compared to my CPU from a few years ago is less than 2x of its single thread performance & 4x its multithreaded performance even though it has 4x the threads.
So realistically Im looking at prolly a doubling of performance by buying the top of the line common CPU available. Almost not worth upgrading, hopefully real benchmarks show larger differences, though I love how AMD are forcing Intel to drop their inflated prices, I would of expected this would hit Intels share value more than it has. Certainly boosted AMDs share price. $2.14 a year ago vs $15.20 today, wonder what bonus the CEO will get (based on the bonuses he used to get when AMD was doing terribly I'm expecting
)
wow shows how little CPUs have improved over the last few years, that CPU compared to my CPU from a few years ago is less than 2x of its single thread performance & 4x its multithreaded performance even though it has 4x the threads.
So realistically Im looking at prolly a doubling of performance by buying the top of the line common CPU available. Almost not worth upgrading, hopefully real benchmarks show larger differences, though I love how AMD are forcing Intel to drop their inflated prices, I would of expected this would hit Intels share value more than it has. Certainly boosted AMDs share price. $2.14 a year ago vs $15.20 today, wonder what bonus the CEO will get (based on the bonuses he used to get when AMD was doing terribly I'm expecting
)
It must be murder Sherlock! :O
It is still essentially DRAM. That means you would be more or less doubling the DRAM access latency, or speculatively parallelising the access (but wasting power and bandwidth while requiring extra silicon).
It is something seemingly nice, but dubiously practical.
Something curious about ryzen and prices in my country is that if I sell my CPU+Mobo+Ram I can get a Ryzen CPU(1600x) with an Asus x370 and 8GBs of ddr4 paying 50 bucks difference and 11 if I go for the 1500.
updating from an I5 4590 with 12GBs to a ryzen 6/12 with 8Gbs or going to a B350 and get 16Gbs 3K is so F*** tempting.... but I would have to sell before R5 came out and have some time W/O a PC plus I would be keeping my very old 7850. But the chances of update my setup basically for free is just crazy...
updating from an I5 4590 with 12GBs to a ryzen 6/12 with 8Gbs or going to a B350 and get 16Gbs 3K is so F*** tempting.... but I would have to sell before R5 came out and have some time W/O a PC plus I would be keeping my very old 7850. But the chances of update my setup basically for free is just crazy...
Anarchist4000
Veteran
Compare it to NVM though. Less static energy and generally slower than standard DRAM. HBM as a cache would be a nice step up in performance. Paging in data, that large of a cache would likely provide a rather high cache hit rate with better overall system performance. Not to mention the possibility of 8(perhaps more?) memory channels. For a Naples chip with 16/32 cores that may be a big deal.
AMD stated already that with the tiny X300 "chipset" (which doesn't do too much) won't use the x4-connection usually reserved for the chipset but will have a separate dedicated link freeing up additional 4 PCIe 3.0 lanes for the use on the mainboard:
That dedicated link could be what looks like the additional two PCIe lanes separate from the two x16 blocks.Robert Hallock said:
Or what is your explanation for that separate PHY which looks exactly like two PCIe-lanes and brings the total count to 34 lanes on the die?
TBH it sounds like X/B/A300 are the marketing names of the integrated FCH. Summit Ridge and Bistrol Ridge themselves are said to be a bootable SoC w/o a southbridge chipset after all. Let alone the fact that the Platform Security Processor is supposed to be integrated as a ring of its anti-tampering measures.
Moreover, 28 lanes do not make sense with the spec being announced. With the presence of the external chipset, the SoC itself provides only x16 + x4. If having a "dedicated link" frees a x4 up, it would be 24 lanes only. 28 lanes are achievable only with X370, which gives eight PCIe Gen 2 lanes on top of the 20 provided by the SoC.
USB, hmm?
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As the X300 is described to be a physically separate chip, this shouldn't be the case.
And a TPM as mentioned by Hallock can (should) still be used even with the ARM based Trustzone environment integrated on chip.
That's indeed an inconsistency. But Robert Hallock may have confused just the total number of available PCIe lanes, not the fact that the usage of the X300 frees up 4 more from the CPU itself compared to the other chipsets. If that is indeed the case, how the X300 "tiny pinky-finger-nail-sized chip" is connected to the socket?
As there are 4 USB interfaces integrated (and not just two) and they support only 5Gbps speed (smaller than 8Gbps PCIe?, another inconsistency with Hallock's claims, btw.), one could suspect the four PHYs in the bottom right third of the die (below the cache portion of the CCX on the right) belong to the integrated USB interfaces.
Having 4x 5Gbps USB3 looking the same as 2x 8Gbps PCIe 3.0 doesn't sound convincing to me.
What should be twice on there are the integrated SATA 6Gbps ports, which can apparently be switched to 8Gbps PCIe 3 operation (for NVMe support, combined with two GP PCIe lanes for 4x NVMe or operating separately as 2x SATA and 2x PCIe/NVMe).
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I'd still take it as a grain of salt, or as a foolproof marketing of "chipsets" without making distinction in integrated vs external. All the bullet points of this "tiny little chip" is essentially what PSP meant to do, especially secure boot. The on-chip boot ROM is the root of trust that spawns the hardware-validated boot process. Having it on a replaceable chipset defies its purpose, and makes it a possible attack vector.
http://images.anandtech.com/doci/9319/Slide 27 - AMD Secure Processor.png
http://www.amd.com/en-us/solutions/desktops/business
Yes the Ryzens consume a bit more power, ~10 watts. Though as this is a desktop thats of very little interest to me, laptop sure.
My observation was just that best CPU one can get today is only about twice the speed of the semi good one I brought 4 years ago
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