AMD RyZen CPU Architecture for 2017

[itsmydamnation]

Yes i would assume that GMI is PCI-E physicals/encoding. I've been looking at die shots trying to get an idea of the possible amount of of PCI-E in the zeppelin dieshot by roughly comparing the relative size of a PCI-E interface to the memory interface. the best comparison i have so far has been to use the good bulldozer die shots and use the HT links as a guess. Each HT 16bit (32bit bidir) link is 76pins. PCI-e 16x is around 160 pins. On Zambezi the HT links are spread thin on mangy-cours they are wider but shorter. it looks like you can get aprox 8 HT interfaces in the same space as the 128bit memory interface (608 HT pins).

On Zeppelin each gmi interface is about 2/3 of the width of the 64bit memory interface but it is about a 1/3 longer, the two GMI interfaces in total would be around the same size as 128bit DDR interface. So that is aprox 608pin which is aprox 64 lanes of PCI-E.

So now the question is how much interconnect between Zeppelin SOC's is enough ? is 16 lanes (25gbps) enough? if so two Zeppelin SOC's could provide 64 lanes to GPU and 32 lanes to motherboard based PCI-E. So long as shortest path is taken between CPU and GPU then the small inter zeppelin GMI link shouldn't be a problem.

On the 32core part a full mesh would leave a total of 64 lanes for PCI-E if its a dual ring then 128 lanes.

So hows that for a mighty long bow! .

 

[3dilettante]

Yes i would assume that GMI is PCI-E physicals/encoding. I've been looking at die shots trying to get an idea of the possible amount of of PCI-E in the zeppelin dieshot by roughly comparing the relative size of a PCI-E interface to the memory interface. the best comparison i have so far has been to use the good bulldozer die shots and use the HT links as a guess. Each HT 16bit (32bit bidir) link is 76pins. PCI-e 16x is around 160 pins. On Zambezi the HT links are spread thin on mangy-cours they are wider but shorter. it looks like you can get aprox 8 HT interfaces in the same space as the 128bit memory interface (608 HT pins).

On Zeppelin each gmi interface is about 2/3 of the width of the 64bit memory interface but it is about a 1/3 longer, the two GMI interfaces in total would be around the same size as 128bit DDR interface. So that is aprox 608pin which is aprox 64 lanes of PCI-E.

So now the question is how much interconnect between Zeppelin SOC's is enough ? is 16 lanes (25gbps) enough? if so two Zeppelin SOC's could provide 64 lanes to GPU and 32 lanes to motherboard based PCI-E. So long as shortest path is taken between CPU and GPU then the small inter zeppelin GMI link shouldn't be a problem.

On the 32core part a full mesh would leave a total of 64 lanes for PCI-E if its a dual ring then 128 lanes.

So hows that for a mighty long bow! .

One item of note when comparing with other AMD chips with PCIe like Carrizo is that the interface PHY is interrupted at intervals by what looks like a controller block.
The Zen shot does not show this, but there is a section of what appears to be individual blocks similar in form on the side of the section. The photo is too grainy to be sure, but it looks like it could be two rows of 4. Carrizo and Kaveri seem to have a block for every 8 sections of the PHY. That may yield the same 64 lanes based on your area estimate.

Going from my interpretation of your scheme for using the Summit Ridge 8-core block is the basis for the Zeppelin 16-core in the APU concept, each 8-core block having 64 lanes each:
This would mean that Greenland would have a much-expanded IO capability versus the GPUs we know today, and depending on whether AMD is giving the GMI link bandwidth in the same unidirectional terms as the DDR4 bus, the links are either within range of PCIe 3.0 or significantly faster. AMD did note "full bandwidth" access to memory, which if taken to the fullest extent would mean unidirectional.

The remaining 32 PCIe lanes does not match the HPC APU slide that offered 64 PCIe lanes, unless there's somewhere else we can borrow the IO.
Could Zeppelin be a different implementation with more lanes, or maybe the HPC APU concept with 64 lanes has been invalidated?

Otherwise, there would need to be a way to link the two 8-core halves without using the GMI section.

For my amusement, I have toyed with the idea of taking the Zeppelin name literally and making a very long die based on two Summit Ridge units and some form of interposer or inter-die link where they are currently separated.
The name would be physically fitting, given how those airships are organized internally.

 

[Blazkowicz]

I can't help but think it's filled with explosive lifting gas to ease the load on rack mounts.

 

[3dilettante]

AMD could market it as the lightest server architecture, and introduce IPC/gram as a new measure.

 

[neliz]

Yes i would assume that GMI is PCI-E physicals/encoding. I've been looking at die shots trying to get an idea of the possible amount of of PCI-E in the zeppelin dieshot by roughly comparing the relative size of a PCI-E interface to the memory interface. the best comparison i have so far has been to use the good bulldozer die shots and use the HT links as a guess. Each HT 16bit (32bit bidir) link is 76pins. PCI-e 16x is around 160 pins. On Zambezi the HT links are spread thin on mangy-cours they are wider but shorter. it looks like you can get aprox 8 HT interfaces in the same space as the 128bit memory interface (608 HT pins).

On Zeppelin each gmi interface is about 2/3 of the width of the 64bit memory interface but it is about a 1/3 longer, the two GMI interfaces in total would be around the same size as 128bit DDR interface. So that is aprox 608pin which is aprox 64 lanes of PCI-E.

So now the question is how much interconnect between Zeppelin SOC's is enough ? is 16 lanes (25gbps) enough? if so two Zeppelin SOC's could provide 64 lanes to GPU and 32 lanes to motherboard based PCI-E. So long as shortest path is taken between CPU and GPU then the small inter zeppelin GMI link shouldn't be a problem.

On the 32core part a full mesh would leave a total of 64 lanes for PCI-E if its a dual ring then 128 lanes.

So hows that for a mighty long bow! .

Terms and conditions apply here. I can't say the same about DP, but let's say it looks really good in a single CPU configuration.

 

[itsmydamnation]

you tease
by DP do you mean dual proc?
and by i cant say the same do you mean you dont know or its not "looks really good".

cheers

 

[neliz]

you tease
by DP do you mean dual proc?
and by i cant say the same do you mean you dont know or its not "looks really good".

cheers

yeah, DP, there's a logical reason for it which will become clearer once people actually talk about how zen works.

 

[itsmydamnation]

yeah, DP, there's a logical reason for it which will become clearer once people actually talk about how zen works.

Thats a worry if there are two socket scaling issues . I completely understand not caring about 4P but 2P is just so common! I wonder if its something like accessing the (rumored) 10gbe thats on SOC across the socket interconnect creating issues? The rumor mill i've seen is 1x10gbe for each compute/l3/nb/gmi cluster that would mean in worst case 40gbe/s of traffic across GMI just to go to the NIC's on the other processor......


edit: atleast with a hypervisor that is something that can be worked around, would be nice is the hypervisor could be NIC location aware.......

 

[Kaotik]

No idea on credibility but...
http://forums.anandtech.com/showthread.php?p=38363321#post38363321

Alkuperäinen kirjoittaja
Zen ES is at the moment in revision A0 - it might not be a suprise.

L2/L3 variations: 2/8 MB, 4/16 MB, 8/32 MB, 12/64 MB, 16/64 MB
(512kb L2/core, 8MB/4 cores)

Core counts are: 4c/8t, 8c/16t, 16c/32t, 32c/64t. As it seems now there won't be a 6c/12t at the launch, there will be only complete core complexes. Later AMD might release a 6/12 version, will see.

AMD's working on 2 kind of packages: AM4 and SP3. Later there might be a SP4 package of course.

4 variants of ES Zen are available at the moment:
AM4 8 cores with 95W TDP
AM4 4 cores with 65W TDP
SP3 24 cores with 150W TDP
SP3 32 cores with 180W TDP

The most exciting part is core clock. The 8c/95W variant's base clock is 2.8GHz, all core boost is 3.05GHz and maximum boost is 3.2GHz.
The 4c/65W part's clock is the same. (I would expect 3.5GHz base clock for a retail 4c/95W variant.)
Idle clock is exciting as well. AM4 versions can lower the clock to 550 MHz in idle which is a very nice level from an AMD CPU. Idle wattage is 5W for 8c version and 2.5W for 4c version.
The SP3 versions have even lower idle clock: it's only 400MHz. Regarding the boost clocks the 32c/180W version has a 2.9GHz boost clock and the 24c/150W version has a 2.75GHz boost clock.

 

[Alexko]

I suppose few definitive conclusions can be drawn from engineering samples (and unconfirmed ones at that) but 3.2GHz for a single core sounds quite low. It's only 200MHz more than a mobile Excavator design on 28nm with HDL. Presumably Zen is also optimized for power and density, but still, I was hoping for about 3.5GHz.

 

[Kaotik]

Regarding credibility of my earlier post, apparently Dresdenboy, who has credit behind him, has confirmed that they're not made up

 

[Grall]

Regarding credibility of my earlier post, apparently Dresdenboy, who has credit behind him, has confirmed that they're not made up

It's cool that Zen seems to work well at A0 rev, but clock speed/power consumption isn't particularly impressive. It's no better than Intel's broadwell-E processors (which use coarser process), but considering disparity in R&D budgets perhaps I shouldn't complain. Also, all socket 2011 chips are anything from rather expensive to ludicrously so; with AMD one might stand a chance of actually owning a 16C/32T chip...

 

[Kaotik]

It's cool that Zen seems to work well at A0 rev, but clock speed/power consumption isn't particularly impressive. It's no better than Intel's broadwell-E processors (which use coarser process), but considering disparity in R&D budgets perhaps I shouldn't complain. Also, all socket 2011 chips are anything from rather expensive to ludicrously so; with AMD one might stand a chance of actually owning a 16C/32T chip...

Though on current plans you're not getting such chip, but have to choose between 8C/16T desktop and 24C/48T server/workstation

 

[eastmen]

It's cool that Zen seems to work well at A0 rev, but clock speed/power consumption isn't particularly impressive. It's no better than Intel's broadwell-E processors (which use coarser process), but considering disparity in R&D budgets perhaps I shouldn't complain. Also, all socket 2011 chips are anything from rather expensive to ludicrously so; with AMD one might stand a chance of actually owning a 16C/32T chip...

A0 rev are always clocked lower for stability. I am sure it will get slightly faster for release. Maybe another 500mhz . But clock speed shouldn't mater if the ipc is high enough

 

[itsmydamnation]

Remember Zen has 10gbe on die ( maybe even a crypto co processor, lots of SATA pci-e etc) so looking at Xeon-D rather then Xeon is more fair. Best perf/watt SKU is 45 watt for 2ghz 8 core with 2x10gbe. Those 32core SOC are rumored to be upto 8x 10gbe ( atleast 4). I dont think power efficiency around a simlar clock speed to Xeon-D is going to be an issue at all, Bigger question is how the clock/power curve scales in to the low-mid 3ghz and if it can get + 4.0ghz if perf/watt isn't cared about for the 8 core SKU.

 

[fehu]

 

[Michellstar]

So finally summit ridge delayed till 2017, no launch this year?

 

[Kaotik]

So finally summit ridge delayed till 2017, no launch this year?

AMD has said all the time that some desktop units should come out in late Q4, but real availability in Q1/17.
(also AMD has previously put products released as early as september of year x-1 for year x in roadmaps)

 

[Michellstar]

AMD has said all the time that some desktop units should come out in late Q4, but real availability in Q1/17.
(also AMD has previously put products released as early as september of year x-1 for year x in roadmaps)

Thanks [emoji1]

 

[fehu]

And now for my next number I need an engineering sample's benchmark from an unreliable source

http://wccftech.com/amd-zen-es-benchmarks/