AMD RyZen CPU Architecture for 2017

[3dilettante]

That Apple is at 14nm is due to TSMC and Samsung.
Samsung's next products in 2016 should have 14nm chips with a custom ARM core.
Samsung's design efforts began to spin up a number of years ago, so we can see that individual projects still take a significant number of years. If an organization is large enough, it can have multiple projects in the pipeline.

 

[iMacmatician]

From Seeking Alpha, "Advanced Micro Devices' (AMD) at Raymond James Technology Investors Conference Transcript." (Emphasis mine.)

So, as Zen, the new x86-based processor; high-end. It's your return potentially into the data center/server area. What's the timing?

Zen was a clean sheet design that started few years ago. We are in the final figure of executing and the milestone that you want hear us talk about is Zen tapping out, which should be over the next several months. And then putting samples in the hands of our customer and then starting portfolio of revenue in 2017.

And by the way, because we have this reuse approach for cores, you will see us with Zen cores in the high-end desktop first and then the server from our overall products standpoint. But the key is tapping out in the next several months, samples and customers for the validation of the product over the 2016 time frame and then the revenue ramp happening in 2016.

I thought Zen already taped out.

 

[Michellstar]

From Seeking Alpha, "Advanced Micro Devices' (AMD) at Raymond James Technology Investors Conference Transcript." (Emphasis mine.)



I thought Zen already taped out.

if i recall, they talked about two finfet tapeouts, but they didn't specify.

we taked for granted that one was zen, who knows anymore...

 

[Alexko]

From Seeking Alpha, "Advanced Micro Devices' (AMD) at Raymond James Technology Investors Conference Transcript." (Emphasis mine.)



I thought Zen already taped out.

I sure hope AMD isn't telling us that just a few months after taping-out, Zen will tap out.

 

[Jawed]

So, Zen beta testing by consumers in a year's time?

 

[iroboto]

[emoji24][emoji24][emoji24][emoji24][emoji24] so long?? Is there no way they can get this chip out before 2017?

 

[eastmen]

wow , I was going to try and hold off till late 2016 to upgrade my cpu to see what zen was about but at this point ehhh...

 

[Entropy]

if i recall, they talked about two finfet tapeouts, but they didn't specify.

we taked for granted that one was zen, who knows anymore...

Quite a few people know, but they are avoiding putting themselves in awkward positions by speaking clearly. We are still a fair distance from actual product being available, things can run more or quite possibly less smoothly from here on out.
People choose from what is available when they need to buy. There is little reason for private individuals to care much beyond that. OEMs are a different story.

If enthusiasts are interested in Zen for purely tech-nerdy reasons, they will simply buy it when it becomes available, and tinker away, discovering the properties of this new entry. No reason to worry much in that case either.

 

[Kaotik]

From Seeking Alpha, "Advanced Micro Devices' (AMD) at Raymond James Technology Investors Conference Transcript." (Emphasis mine.)
I thought Zen already taped out.

I'm thinking taping out what will be actual final products, different configurations etc?

 

[tunafish]

Well, very few CPUs ship (or indeed, are even marginally functional) on A0 silicon, so they could have taped out Zen A0, validated it, and are hopeful of taping out a version that can go into production soon. However, that's not how the phrase is usually used. I don't think much can be concluded about the information we currently have.

 

[3dilettante]

If 2017 is to be AMD's return to the server market, then the silicon for whatever chip goes into that range would be undergoing a longer validation cycle on top of the validation that would go into a desktop product.
Some of AMD's other server products had very long lag times, which on one hand were due to issues besides the required validation, and on the other AMD usually gets those. It would be a push in the best case scenario.

I hope another enablement patch comes out for Zen soon-ish. A rough time frame has been posited by comparing the introduction of other AMD architectures' patches and their launch. Zen's patch has some very large gaps in it compared to how thorough AMD's descriptions were in the past, which makes me uncertain that this data point is like the others.

 

[fehu]

I've read a rumor about a 2016 (not 2017) zen based apu with a single channell HBM1 and a bigger gpu
Considering the raw flops of actual carrizo, it can be in the Xone's level and very cheap, so... nx?
But hbm1? and ready in 2016?

 

[Kaotik]

I've read a rumor about a 2016 (not 2017) zen based apu with a single channell HBM1 and a bigger gpu
Considering the raw flops of actual carrizo, it can be in the Xone's level and very cheap, so... nx?
But hbm1? and ready in 2016?

In theory everything is of course possible, but AMD's own roadmaps say it's Bristol Ridge (Carrizo) for 2016

 

[Deleted member 13524]

If by "single-channel HBM1" they actually mean "single stack", then AFAIK with HBM1 the APU would be limited to a 4-Hi stack of 1GB at 128GB/s:

Although the bandwidth seems fine for an APU, it wouldn't be terribly useful if all it had was 1GB of total RAM, meaning it would need additional external memory.

HBM2 would allow 4x the density and a 8-Hi stack, so 8GB tops. That would be plausible but probably a very expensive/risky solution for 2016, especially for Nintendo.

Moreover, Zen doesn't seem aimed towards consoles at all, since AMD even decided to sell it as a "pure" CPU first in order to avoid delays related to adding a GPU and southbridge functionality into its first models.

 

[AnarchX]

1GB HBM1 is probably a safer bet for a 2016 sampling and 2017 launching APU, with <$250 price target, than HBM2 which was specified some days ago.
If you put just BW-demanding buffers in the 1GB you can feed a ~1024SPs iGPU. Long term HBM2 will be used, with 8-16GB you also can drop your DDR4 external RAM and let the APU feed from your 1-2GB/s SSD.

 

[Deleted member 13524]

But what's the point in using HBM rev.1 during late 2016/2017, when rev.2 is set on stone as a JEDEC standard?
I see no inherent reason to believe rev.1 is substantially cheaper to produce than rev.2.
Samsung is only producing HBM rev2 chips and I doubt Hynix will continue producing rev1 for much longer (even Fiji may get an upgrade to rev.2).

 

[function]

It could be that they're getting a really good price on HBM1 as Hynix was to recoup at least some of their investment, and that for a 128GB/s solution this is cheaper than HBM2. 1GB will be plenty to greatly accelerate integrated graphics, and any APU that AMD release and any socket it's on will realistically have to support DDR4 as well.

It's also possible that the APU design was locked down before the HBM2 spec was finalised and availability timescales for it were known.

 

[Blazkowicz]

Moreover, Zen doesn't seem aimed towards consoles at all, since AMD even decided to sell it as a "pure" CPU first in order to avoid delays related to adding a GPU and southbridge functionality into its first models.

Isn't there southbridge functionality anyway? I believe socket AM4 is made like AM1 in that regard. Everything plugged into it will be a SoC that includes the basics like USB, SATA, ethernet and a handful little things.

 

[Kaotik]

There has been some slides and parts of slides going around about the supposed HPC APU, which would feature "Zeppelin CPU" and "Greenland GPU" on MCM package with some HBM2 and 4x DDR4 channels
The Zeppelin CPU is now confirmed to be real
http://dresdenboy.blogspot.de/2016/02/amd-zeppelin-cpu-codename-confirmed-by.html

The current numbers there would allow up to 32 cores (64 threads), while the slides have mentioned just 16 cores (32 threads)

 

[tunafish]

The current numbers there would allow up to 32 cores (64 threads), while the slides have mentioned just 16 cores (32 threads)

Note that 32 is just the max amount of cores per socket that the current core id system allows. This doesn't mean that they actually intend to build a chip like that. On the other hand, if they wanted to make a bigger one, changing the system wouldn't be that hard. So doesn't really provide any hard information. At most, you can take it to mean that some engineer at AMD thought that 32 ought to be enough for this generation.

The more interesting part is the (older, but I didn't notice that patch at the time) confirmation that LLC now lives among cores, not on the NB which likely has latency implications. I wonder if writes from a core preferentially access their own L3 slice or if they do a system similar to Intel where each cache line belongs to a specific L3 slice depending on it's address, and all cores access all L3 evenly.