A Survey Of Architectural Techniques for Managing Process Variation
Accepted in ACM Computing Surveys 2016
Part of the abstract:
Process variation --deviation in parameters from their nominal specifications-- threatens to slow down and even pause technological scaling and mitigation of it is the way to continue the benefits of chip miniaturization. In this paper, we present a survey of architectural techniques for managing process variation (PV) in modern processors. We review PV management techniques in CPU, GPU, different processor components (cache, main memory, processor core) and different memory technologies (SRAM, DRAM, eDRAM, NVM) etc.
The aim of this paper is to provide insights to the researchers into the state-of-art in PV management techniques and motivate them to further improve these techniques for designing PV resilient processors of tomorrow.
Accepted in ACM Computing Surveys 2016
Part of the abstract:
Process variation --deviation in parameters from their nominal specifications-- threatens to slow down and even pause technological scaling and mitigation of it is the way to continue the benefits of chip miniaturization. In this paper, we present a survey of architectural techniques for managing process variation (PV) in modern processors. We review PV management techniques in CPU, GPU, different processor components (cache, main memory, processor core) and different memory technologies (SRAM, DRAM, eDRAM, NVM) etc.
The aim of this paper is to provide insights to the researchers into the state-of-art in PV management techniques and motivate them to further improve these techniques for designing PV resilient processors of tomorrow.