The AMD Execution Thread [2007 - 2017]

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In that period more work has gone through the Semi-Custom business which does not go through the R&D spend reporting, but is NRE directly billed to the customer. Not only does this take out any of the "development" portion of the costs, but the last console launches highlighted that there was IP pull/pooling between AMD's own products and those developed for direct semi-custom customers

http://seekingalpha.com/article/3044856-amds-rapidly-declining-r-and-d-myth
 
AMD lost significant market share to NV in the PC gaming market, even though Sony/MS foot the bill for GCN R&D, highlights that this "hidden" R&D money might not serve AMD's interest any more than Sony/MS's.

How does this improves the outlook of long term development of core products, with architecture portfolio designed with/tuned to the interest of many diverse clients in mind?
 
Per my very limited accounting knowledge, NRE revenue paid by semi-custom customers would not be counted against the cost of final products sold, since it is an upfront cost instead of the related unit cost (either direct or indirect) of manufacturing the final products (processor SKUs). In other words, given that AMD's sheets do not list them as a separate revenue, it is very likely collapsed into AMD's corporate R&D expenses - say the R&D expense reported is lowered than the actual expense by the amount of the NRE revenue they were paid.

AMD's CPU, graphics and system IPs should still worth something. So I believe on top of the SoC design cost and customisation, licensing fee to the IPs would also be paid as an NRE package. Then those licensing fee would be the additional fuel to the future IP development.
 
AMD lost significant market share to NV in the PC gaming market, even though Sony/MS foot the bill for GCN R&D, highlights that this "hidden" R&D money might not serve AMD's interest any more than Sony/MS's.

How does this improves the outlook of long term development of core products, with architecture portfolio designed with/tuned to the interest of many diverse clients in mind?
Customers are coming this route because of the core IP AMD have developed, or is under development, that they want in specific configuations/implementations - they are not coming at this asking to implement a clean slate of IP as thats not cost effective. In effect they are AMD IP licensing, but the customer is paying for a specific implementation (chip) that suits their needs.

Given thats the case synergies beteween the customers target and AMD's core products are likely to be high from the outset - yes, there may be some specific implementation tweaks (i.e. EDRAM on XBOX One) but for the most part the CPU and Graphics IP were the same between console and AMD's PC products. And while developments that start out as a request from a customer may ultimately end up being useful in AMD core products; as a hypothetical, lets say that it was it was a semi custom customer that requested ACE engines, that while it wasn't much use for AMD iinitially it is now having benefits with DX12, which AMD has input into shaping.
 
If AMD released an APU more powerful than the one they put in PS4, I'd buy it, but I swear they must have an agreement with Sony that they won't do that.
 
zen apus got postponed until 2017, to get better performance than liverpool they need GDDR5 or HBM.

At some point, if i recall Kaveri was supposed to have an GDRR5 controller but was axed
 
And unless socket FM3 supports APU packages with HBM included, AMD will need yet another socket if they want a high-performing APU with Zen.
 
And unless socket FM3 supports APU packages with HBM included, AMD will need yet another socket if they want a high-performing APU with Zen.
The alleged spec is an MCM package of a CPU and an HBM GPU anyway, and they can just make it available in BGA package for machines that really can take advantage of it (hola iMac, eh, if HSA or Metal for Compute becomes a thing on OSX). DIY PIB doesn't seem a nice place to land such a thing.
 
If even Intel decided to produce and sell socketable MCM packages with APUs and EDRAM, you can bet that market is a "nice place".
 
AMD faces suit over alleged misrepresentation of new CPU

One of the world’s largest computer chip manufacturers is facing a lawsuit over allegations of deceptive marketing.
In claiming that its new Bulldozer CPU had “8-cores,” which means it can perform eight calculations simultaneously, AMD allegedly tricked consumers into buying its Bulldozer processors by overstating the number of cores contained in the chips. Dickey alleges the Bulldozer chips functionally have only four cores—not eight, as advertised.

The suit alleges AMD built the Bulldozer processors by stripping away components from two cores and combining what was left to make a single “module.” In doing so, however, the cores no longer work independently. As a result, Dickey argues that AMD’s Bulldozer CPUs suffer from material performance degradation, and cannot perform eight instructions simultaneously and independently as claimed. He alleges that average consumers in the market for computer CPUs lack the requisite technical expertise to understand the design of AMD's processors and trust the company to convey accurate specifications regarding its CPUs. Because AMD did not convey accurate specifications, Dickey argues that tens of thousands of consumers have been misled into buying Bulldozer CPUs that cannot perform the way a true eight-core CPU would.

http://legalnewsline.com/stories/510646458-amd-faces-suit-over-alleged-misrepresentation-of-new-cpu
 
"Dickey argues that AMD’s Bulldozer CPUs suffer from material performance degradation, and cannot perform eight instructions simultaneously and independently as claimed."

Dickey's gonna have to come up with a better claim than that.
 
Actually, BD is able to perform (i.e. retire) 8 instructions per clock (referring to the main argument), since there are 8 completely duplicated x86 integer cores, that are capable of pipelined execution. The FPU isn't counting in since it's technically still a separate co-processor ISA in relation to the x86. Same for the front-end (fetch and decode), despite the fact that most of it is statically partitioned between the threads.
 
It's probably accurate to say that Bulldozer can't run 8 FP instructions per cycle. However, there's no rule requiring that a "core" must be able to run at least one FP instruction per cycle. Some CPU don't even have a FPU, others have non-fully-pipelined FPU so they can only run one FP instruction per two cycles.
I'm pretty sure that AMD never claimed that Bulldozer have 8 FP cores. So IMHO the lawsuit is without basis.
 
The chip in question appears to be an 8-core implementation, which should hit 8 or higher for various instructions. Fetch/decode is 16, FMA is 8, Integer SIMD is 8, integer is 8/16, load/store is 16, etc. The FPU is capable of having instructions in-flight from either core.
The FPU only falls short if considering AVX-256, but it seems like a stretch to declare that an 8-core chip be capable of executing at full throughput every instruction of every type in every mode.

I do not know to what amount AMD can appeal to the basic definitions of the art when arguing against the suit. Unless Bulldozer was electrically and physically incapable of independent processing from 8 threads, I am not sure where the chip would fall down on this.
Maybe AMD can have the suit dismissed, or settle out of court for a copy of Hennessy and Patterson.
 
The chip in question appears to be an 8-core implementation, which should hit 8 or higher for various instructions. Fetch/decode is 16, FMA is 8, Integer SIMD is 8, integer is 8/16, load/store is 16, etc. The FPU is capable of having instructions in-flight from either core.
The FPU only falls short if considering AVX-256, but it seems like a stretch to declare that an 8-core chip be capable of executing at full throughput every instruction of every type in every mode.

I do not know to what amount AMD can appeal to the basic definitions of the art when arguing against the suit. Unless Bulldozer was electrically and physically incapable of independent processing from 8 threads, I am not sure where the chip would fall down on this.

It seems to me that the burden should be on Dickey to prove that the basic definitions of the art are somehow at odds with AMD's claims.

Maybe AMD can have the suit dismissed, or settle out of court for a copy of Hennessy and Patterson.

:LOL:
 
It's probably accurate to say that Bulldozer can't run 8 FP instructions per cycle. However, there's no rule requiring that a "core" must be able to run at least one FP instruction per cycle. Some CPU don't even have a FPU, others have non-fully-pipelined FPU so they can only run one FP instruction per two cycles.
I was reminded of the UltraSPARC T1 which is an 8-core processor with only one FPU.
 
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