LSI or Samsung mobile
***edit: if there's nothing else wrong on the tablet here, 2GB devices should run out of memory at about 10 Manhattan runs in a row.
I find the Qualcomm news to be huge as a precedent for the future. Their modems had become an almost-requirement for the U.S. market.
With their in-house capabilities, Samsung doesn't have much need to look back for many future phones (though I'm sure Qualcomm will fight tooth-and-nail for design wins in Samsung's line-up.) And, maybe, the cost structure of their "in-house" SoC supply will finally have them seeing decent cost savings with Exynos versus outsourcing.
Other OEMs have been dabbling in SoC design, too. And MediaTek is still picking up momentum in Western markets.
Qualcomm finally ran out of the lessening thermal headroom they'd been leaving themselves each generation since like the S4 Pro/S600 to have given Samsung enough incentive to stay Exynos. Obviously, the effects on Qualcomm's bottom line will remain limited at first, but I don't see this as just some blip, soon to be forgotten in the Snapdragon story. I think the competitive landscape gets much more difficult for them here on out, and their follow-up designs will need to be something special indeed to turn the tide back. I don't see them losing their spot as the industry's Number One Supplier, but the monopoly will finally go away.
It still pretty much is a requirement. The CDMA variants on Verizon on Sprint still use a Qualcomm modem due to simple lack of alternative.I find the Qualcomm news to be huge as a precedent for the future. Their modems had become an almost-requirement for the U.S. market.
Don't believe everything you read on the internet.
Don't know, but given the 28nm and only 1.8GHz clock on that rumoured piece it seems like a perfect mid-range SoC even if it has A72 cores. You're throwing a bit more money on die size but by that time 28nm will get dirt cheap.I find a bit hard to believe a Snapdragon 600 series would bring a new A72 core while the 800 series are still using the A57.
Snapdragon 615 uses eight Cortex A53, with one of the quad-core modules being more performance-optimized (higher-clocked) and the other module being power-optimized.
The performance jump from S615 to S620 would be enormous..
A couple of designs that I do not understand from Qualcomm's lineup.
(4 x A53) + (4 x A53) -> This is what we often hear as proof of certain region's preference for moar cores. But is that really true or is it simply a Qualcomm's excuse? Are there really benefits of Global Task Switching (or whichever big.LITTLE inner-working) for this configuration?
(2 x A57) + (4 x A53) -> I do not understand this design, either. Why introduce an imbalance that is seemingly unnecessary, assuming proper power-gating? If power is really the reason, wouldn't (2 x A57) + (2 x A53) design make more sense?
Why haven't we seen 2+2 big.LITTLE yet?
The problem with 2+4 big.LITTLE is that it's more expensive than 4+4 little.LITTLE and it's not as good marketing-wise. This is why I quite like the idea of 2+4+4 big.little.LITTLE as I suggested regarding Denver+A53 (but the same applies to A72+A53/[...]).
Because A57 is more than 2x the size of A53 afaik. Of course the difference isn't as big as it was for A7 vs A15; who knows about A72...Why is 2+4 more expensive than 4+4? (honest question).
Because A57 is more than 2x the size of A53 afaik. Of course the difference isn't as big as it was for A7 vs A15; who knows about A72...
Don't know, but given the 28nm and only 1.8GHz clock on that rumoured piece it seems like a perfect mid-range SoC even if it has A72 cores. You're throwing a bit more money on die size but by that time 28nm will get dirt cheap.
You'd certainly think that a 2+4 big.LITTLE ought to be a good chip for mid to high-range device. Plenty of performance available from the two big cores when required and decent performance from the 4 little ones with a good reduction in die size as well.
However, it seems that the mid-range has instead been taken up by the 4+4 A53 (and previously A7) options. My phone uses a 4+4 A7 Mediatek chip and it provides perfectly capable performance. A little bit faster would be nice, but certainly no problems to speak of. Personally, I wonder when (or if) we'll see a bit more memory bandwidth find its way into mid-range devices which all use single-channel LPDDR3 at the moment.
The problem with 2+4 big.LITTLE is that it's more expensive than 4+4 little.LITTLE and it's not as good marketing-wise. This is why I quite like the idea of 2+4+4 big.little.LITTLE as I suggested regarding Denver+A53 (but the same applies to A72+A53/[...]).
Because A57 is more than 2x the size of A53 afaik. Of course the difference isn't as big as it was for A7 vs A15; who knows about A72...
If SMIC (which has been rumored to be the target foundry of some of these mid-low range SoCs for Qualcomm) or UMC have viable 20nm. Remember Nvidia saying that 20nm transistor cost doesn't go down compared to 28nm. I know they have to do double patterning at 20nm, so maybe 28nm will still remain cost-effective, and that's indeed what a lot of people have been saying in the industry.By 2016 you would expect 20nm to be below 28nm in per transistor cost..and A72 is power hungry..so 20nm seems like a better choice.
By 2016 you would expect 20nm to be below 28nm in per transistor cost..and A72 is power hungry..so 20nm seems like a better choice.
and A72 is power hungry..so 20nm seems like a better choice.
If SMIC (which has been rumored to be the target foundry of some of these mid-low range SoCs for Qualcomm) or UMC have viable 20nm. Remember Nvidia saying that 20nm transistor cost doesn't go down compared to 28nm. I know they have to do double patterning at 20nm, so maybe 28nm will still remain cost-effective, and that's indeed what a lot of people have been saying in the industry.
I might be wrong but it looks like all of the studies that claim such things come from the same source: a projection from IBS. Has any other analysis been published?Haven't you got the multiple message yet that 20nm will be more expensive than 28nm per transistors?
Look here for example: www.bnppresearch.com/ResearchFiles/31175/Semiconductors-230414.pdf