what is the current state of NV50 ?

With the NV40 almost certainly finished by now (probably a long time ago) and going through the usual revisions, awaiting production, likely being on shelves in the March-April timeframe, what would be the current state of NV50 ?

probably we won't see NV50-based products in 2004, maybe not until fall 2005, although there is no doubt it is deep into development now...has been for quite some time, has it not?
 
I wonder if it's still being run through those really nifty simulators they have running in their huge server farm.

I think I remember there was an article on a particular programmable simulation device that they use to model the chip, though I think it was mentioned that they don't port the architecture into one of those units until it gets through the farm first.

I don't know if they've gotten to the point of any test spins, since maybe the nv45 needs to go through first, assuming nv40 has gotten beyond that stage.
 
I think it is a bit fruitless to discuss NV50 before we have any hints on NV40. I see no news or noteworthy facts about what NV40 actually is. Thinking of NV50 is like multiplying that feeling of no info I have by 10^10.
 
yes nv50 is at the servers farm well at least as of a three months ago ... i know becouse i saw a video of the farm on the tour guide had said something about it ....just wish i could find the link



rets
 
3dilettante said:
I wonder if it's still being run through those really nifty simulators they have running in their huge server farm.

I think I remember there was an article on a particular programmable simulation device that they use to model the chip, though I think it was mentioned that they don't port the architecture into one of those units until it gets through the farm first.
The hardware simulators used by both Nvidia and ATI are called IKOS boxes (named after the company IKOS Systems Inc) . The latest and greatest IKOS box is linked here.

AFAIK, the IKOS boxes are used moreso to test device drivers for the upcoming asic before any silicon comes back. This is because attempting to boot into Windows or test 3D games on a software emulator is rediculously slow (ala refrast for DX9).
 
The IKOS box is listed to be capable of handling 120 million transistors in simulation. I wonder if more than one can be linked together, otherwise I don't see how an NV35 with 135 million (I think) could have been run through.

I wonder what they do with something like 170 million for upcoming cores.
 
Tahir said:
I think it is a bit fruitless to discuss NV50 before we have any hints on NV40. I see no news or noteworthy facts about what NV40 actually is. Thinking of NV50 is like multiplying that feeling of no info I have by 10^10.
What? No NV40 info? What type of real deep hole have you been hiding in? :p

Here are 10 "NV40 facts" ( okay, some are not 100% sure, but some seem pretty darn reliable to me, I'd be surprised if 60% of it wasn't right )

NV40
---
1) 600Mhz core on IBM's 0.13u technology, 48GB/s memory bandwidth with 256-bit GDDR2
2) 8x2 ( possibly 16x0 or 16x1 mode, although I'd find that rather stupid personally due to the focus on AA ).
3) FP32/FP16/FX16, this means PS1.4. is done in FX16 100% legally, while it would seem logical for PS2.0. partial precision to be done in FP16 unless MS decides to expose the HW better in an upcoming DX9 revision.
4) ( unsure ) HUGE die, NVIDIA is most likely artificially increasing die size to make cooling more efficient.
5) Slightly beyond PS3.0. / VS3.0. specificiations ( not anywhere as much as PS2.0.+ and VS2.0.+ were compared to the PS/VS2.0. standard though, I assume ).
6) Support of a Programmable Primitive Processor
7) The only units being shared between the VS and the PS are the texture lookup units ( NOT addressing units; addressing is still done on a standard FP32 unit ).
8 ) Most likely no 512MB version, that's still overkill IMO.
9) PCI-Express support, most likely ( but not certainly ) through a compatibility bridge between AGP and PCI-Express.
10) Completely new AA algorithm, most likely a stochaistic(sp?) approach.
---
Release: February-March 2004

And when it comes to the NV50...
---
1) Full ILDP; sharing of VS/PS units
2) 0.09u most likely
3) Not a TBDR!
---
Release: Mid 2005, most likely ( SIGGRAPH? )


It's not because GPU:RW isn't online anymore that it means we don't know anything about NVIDIA's next gen products ;) :p :)


Uttar
 
Brimstone said:
How will programers utilize the PPP? I thought it was impossible with DX 9?
At least HOS and tessellation in several flavors may be supported, but no programmability. That will be restricted to OpenGL

If it's in, it's probably rather limited, like a "first try" anyway.
 
Xmas said:
If it's in, it's probably rather limited, like a "first try" anyway.

Agreed. Although it most likely isn't THAT limited; it was already on the NV30 wishlist ( got scrapped, probably rather fast too, but not sure about that type of details ) - so I assume that even if it's the first time they implement it in hardware, they must have had a loooong time to think about it ;) Not that this helps much...

Good idea about DX9 exposing it through its non-programmable HOS capabilities :) Was wondering how they'd do it. Actually, maybe if the original R400 had been released, which also had a PPP, then MS would have bothered to expose it entirely in an API revision. A tad late for that now, though :)


Uttar
 
What? No NV40 info? What type of real deep hole have you been hiding in?

Here are 10 "NV40 facts" ( okay, some are not 100% sure, but some seem pretty darn reliable to me, I'd be surprised if 60% of it wasn't right )

NV40
---
1) 600Mhz core on IBM's 0.13u technology, 48GB/s memory bandwidth with 256-bit GDDR2
2) 8x2 ( possibly 16x0 or 16x1 mode, although I'd find that rather stupid personally due to the focus on AA ).
3) FP32/FP16/FX16, this means PS1.4. is done in FX16 100% legally, while it would seem logical for PS2.0. partial precision to be done in FP16 unless MS decides to expose the HW better in an upcoming DX9 revision.
4) ( unsure ) HUGE die, NVIDIA is most likely artificially increasing die size to make cooling more efficient.
5) Slightly beyond PS3.0. / VS3.0. specificiations ( not anywhere as much as PS2.0.+ and VS2.0.+ were compared to the PS/VS2.0. standard though, I assume ).
6) Support of a Programmable Primitive Processor
7) The only units being shared between the VS and the PS are the texture lookup units ( NOT addressing units; addressing is still done on a standard FP32 unit ).
8 ) Most likely no 512MB version, that's still overkill IMO.
9) PCI-Express support, most likely ( but not certainly ) through a compatibility bridge between AGP and PCI-Express.
10) Completely new AA algorithm, most likely a stochaistic(sp?) approach.
---
Release: February-March 2004

And when it comes to the NV50...
---
1) Full ILDP; sharing of VS/PS units
2) 0.09u most likely
3) Not a TBDR!
---
Release: Mid 2005, most likely ( SIGGRAPH? )


It's not because GPU:RW isn't online anymore that it means we don't know anything about NVIDIA's next gen products


Uttar


thanks Uttar 8)


forgive my ignorance, but what is ILDP and what can you do with it?
 
3dilettante said:
The IKOS box is listed to be capable of handling 120 million transistors in simulation. I wonder if more than one can be linked together, otherwise I don't see how an NV35 with 135 million (I think) could have been run through.

Ah, but in that link, the V-Station Pro scales to 120 million gates. Typically a gate for logic takes 5-7 transistors, so the box is capable of simulating about 700+ M transistors of logic... More than enough for anything up Nvidia's sleeve!
 
3dilettante said:
The IKOS box is listed to be capable of handling 120 million transistors in simulation. I wonder if more than one can be linked together, otherwise I don't see how an NV35 with 135 million (I think) could have been run through.

I wonder what they do with something like 170 million for upcoming cores.

In a highly parallelised environment do you alway need to simulate the entire chip?
 
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