Are those directly related to their capability to transmit two data pulses per clock ?
Not necessarily. The PLL is there to decouple the system from the memory system. The DLL is used to move the incoming capture clock such that the incoming data can be clocked at a stable moment.
I'm rusty on this and may be making a fool of myself, but I believe it went like this:
For reads, the DQS/DQSn differential pair carries the clock, is driven by the RAM and changes at the same time as the data bits. Internally, you should clock the data when things are stable, in the middle of the data eye. For DDR, that means that the phase relation between clock and data needs to be shifted by 90 degrees. The DLL does that for you.
DDR does not require a DLL. If your clock has a decent duty cycle is a nicely tuned to change in the middle of the data eye, you can use a falling and rising edge FF or a double rate clock and that's it. The problem with DDR DRAM is that they are dealing with insanely high clock speeds and that the speeds are not constant.
For writes, the DQS/DQSn is driven by the MC instead of the RAM. So the data always has a source synchronous clock that runs with it. There is 1 DQS/DQSn pair per 8 or 9 bits. The routing delay between different byte lanes doesn't have to be as closely matched as the intra-byte routes.
There may be some things wrong in my explanation, but you get the general idea: the DLL is there to force a certain relationship between clock and data.
Fundamentally, there is not a big difference between SDR and DDR: the only real difference is the transmit and receive logic inside the IO pads. Other than that, you can treat it internally as a double wide SDR.
E.g on the transmit side, DDR is not much more than 2 flip flops with a mux after it that's controlled by the clock.