Xbox One (Durango) Technical hardware investigation

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Sorry, but that's a lousy link to that article as you fail to convey the key info.
XB1 ESRAM gains significant 88% BW increase to 192 GB/s theoretical peak.

Although reading the article, that's not quite right. It's actually a case of
MS Engineers stumble across gains in the ESRAM performance allowing higher BW to devs.


Remember, kids, don't just read the titles to understand an article. ;)
Does not say much for MS hardware engineers if they only figured this out now.
 
Is ridiculous.Maybe they find next time that from production came 14 CUs instead of 12.Wasnt Richard from DF a technical journalist?.
Or the final hardware is a somewhat more capable than old documents suggested, and they wanted to get that out there.
 
The interface width is 128 byte. If the clock is 800 Mhz, there no way you can exchange more data than 102 Gb/s. If indeed this news is true, then they may have changed the clock of the interface and/ or only of the ROPs... running at double the GPU frequency? Than, in the same GPU cycle, you could read and write simultaneously.
 
Using fantasy land mathematics, yes, more than 200


Sigh, there is nothing fantasy about it. 200 gb/s can be moved through the memory units simultaneously. It is just that the data needs to be split into at least two pools for that to happen - 1 main memory and 1 esram. MS even highlight the type of work loads that are best suited for esram.
 
Is the same.The 102GB/s is read 102GB/s write.They found out now that both can be done simultaneously?.

From the DF article, it sounds like they can do read and write together under some circumstances (when they found some "holes" to squeeze some processing inside).
 
Sorry, but that's a lousy link to that article as you fail to convey the key info.
XB1 ESRAM gains significant 88% BW increase to 192 GB/s theoretical peak.

Although reading the article, that's not quite right. It's actually a case of
MS Engineers stumble across gains in the ESRAM performance allowing higher BW to devs.

Remember, kids, don't just read the titles to understand an article. ;)


So, they're adding the read and write bandwidth together. Isn't that sort of ... dumb. That's basically the same specs we had before, just added together to look better. I thought Digital Foundry was a little bit better than that.
 
From the DF article, I sounds like they can do read and write together under some circumstances (when they found some "holes" to squeeze some processing inside).

In fact isnt this news talking about a downgrade?. If clock was still 800Mhz the theorical max bandwidth if writing and reading at the same time would be 204 GB/s.They claim 192 that reversing would take us to 96 GB/s read 96 GB/s write and a clock of 750MHz.
 
From the DF article, I sounds like they can do read and write together under some circumstances (when they found some "holes" to squeeze some processing inside).

On the same 128 byte interface how can you transfer more information than what is theoreticaly possible? Because this is what we are talking about.
 
In fact isnt this news talking about a downgrade?. If clock was still 800Mhz the theorical max bandwidth if writing and reading at the same time would be 204 GB/s.They claim 192 that reversing would take us to 96 GB/s read 96 GB/s write and a clock of 750MHz.

I have no idea but I am just wondering why can't they post a higher test result if they can go 192.

It's believed that 133GB/s throughput has been achieved with alpha transparency blending operations (FP16 x4).

Perhaps some conditions need to be "aligned" ?
 
Bidirectional bus? It doesn't make a lot of sense. Peak theoretical hardware limit is bus*clock. Can't get past that. If the bus is bidirectional by design, you'd get double peak BW. The key info in the DF article is 'holes', which means nothing to me.

It does match what Cranky's said, though, that with 133 GB/s realistic BW, plus 68 GB/s DDR3, we get the 200 GB/s of the E3 conference. I just can't see what the hole is and how it gets filled. :???:
 
Maybe they have alpha blending logic on the ESRAM, similarly to the Xbox 360 (but without MSAA or depth-testing support). If this is the case, the GPU <-> ESRAM bandwidth might still be 102.4 GB/s, but a single-pixel read-modify-write cycle for alpha-blending is performed on the ESRAM, without the need to move the data back to the ROPs. So it might be that the engineers of course already knew of this feature, but they didn't take it into account in the performance figure provided earlier to the developers.
 
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