The mobile chip makers and Intel have so far lived in spaces that didn't intersect too much, only due to Intel's refusal/ineptness (take your pick) to really trade off performance for low power.
I don't think they refused because of the tradeoff. I think they refused because margins were too low to bother with and they didn't want to cannibalize higher end sales. Atom could have arrived a long time ago, but Intel resisted and it only came about because Intel saw a threat from Via and AMD in grabbing low end marketshare. It was a really half-assed effort at first, but enough to keep competitors at bay. I think it still sees the phone SoC market as too low margin, but they see some light down the road as more complex apps get run on them so they're putting a foot in.
So this raises the question of the origin of the latest leak...
I suppose, but we've seen all to many fabrications to get page hits, so who cares.
To clarify: 7W is for what Intel calls SDP, not their usual TDP (which is 13W). Interestingly Techreport forgot to mention that
I don't think that's as misleading as you make it out to be:
http://hothardware.com/News/Intel-Confirms-New-7W-Ivy-Bridge-Chips-Haswell-Parts-To-Follow/
I found
an anandtech post from someone who plotted Sandy Bridge power consumption from a constant workload and frequency as a function of Tj (adjusted through varying airflow over a heatsink), and there's a relationship that suggests HotHardware is right. I'm guessing that this curve gets relatively steeper for low power parts, since it's due to thermal dependence of leakage power, which is more meaningful for low power IvB variants.
If there's enough cooling to keep these chips at or below 80 degC, then they shouldn't consume more than 7W. If you skimp on the cooling, then power consumption will rise probably to the point of causing thermal runaway (up to the throttle point). I say this because I'm pretty sure that if a cooling solution can't dissipate 7W @ 80C, then it probably won't be able to dissipate 10-13W @ 105C. That's probably why the latter is what you design the cooling solution to, and if you do so, then power draw won't exceed 7W.
If this is all correct, then I think SDP is a fair metric for these chips.