Go on record and predict Sony and Microsoft next generation systems specifications

In my opinion,it seems quite "accurated".(except maybe memory layout ps4 ..I'm going with 192GB/sec and some stacked level for 4GB GDDR5..)

I'm surprised anyone would think so. I made a lot of outlandish Durango assumptions and no one else is guessing the process will be FD-SOI.

Also, if you're going to go stacked, you can easily make it wide enough to get that bandwidth from DDR3. So I think it's one or the other, WideIO with stacking, or 256 bit traditional bus to GDDR5.
 
I'm surprised anyone would think so. I made a lot of outlandish Durango assumptions and no one else is guessing the process will be FD-SOI.

Also, if you're going to go stacked, you can easily make it wide enough to get that bandwidth from DDR3. So I think it's one or the other, WideIO with stacking, or 256 bit traditional bus to GDDR5.


I followed your assumptions about FD-SOI for being the most likely path by soiconsortium.org. *(assuming Sony and MS,TSMC,global foundries etc follow this route..)

*
http://www.soiconsortium.org/fully-...na - 28 & 20nm FDSOI Technology Platforms.pdf

I'm fully agreed with you ...about some "stacked level" the term its not correct in my post ... I imagined something like "direct paths" more customized for apus+gpu and GDDR5 commonly see in closed box... and indeed stacked 2.5D to 3D** something like DDR3(512Bit or even 1024Bit) its more probably for this kind of paradign.

**
3322d1334001574-riko2.jpg


http://www.semiwiki.com/forum/content/1161-edps-3d-ics.html
 
In my opinion,it seems quite "accurated".(except maybe memory layout ps4 ..I'm going with 192GB/sec and some stacked level for 4GB GDDR5..)

When you stack ram, there's no point in using a complex and expensive bus standard like GDDR5. In 5Gbps GDDR5, the actual ram chips run at ~310 MHz. GDDR5 adds a very complex and rather expensive layer on top of that so that you can use many of them in parallel on as few pins as possible, by signaling at 16x the speed and pulling data from 16 sources at the same time. The reason for this is that wires on motherboard are rather expensive. This costs die area on the memory chip (way less than half of a GDDR5 chip is in the memory arrays, most of it is in the interface), die area on the GPU, and, most importantly, a lot of power because driving a signal at 16x speed costs a lot, lot more than driving 16 low-speed signals.

Once you stack, on an interposer or directly on the logic, more wires no longer cost that much more. When the difference between 1k pins and 4k pins is not that bad, you want to use low-speed memory with a really wide interface instead of very fast ram.

No-one is going to ever stack GDDR5.
 
As I'm reading this, I'm a little perplexed by many of the responses.

Hasn't it already been pretty much said that IBM is doing XBOX 3's CPU again?
Why are many of you saying it's going to be AMD now? :?:
 
I hope you're missing a smiling face there. LOL If not you're behind the times. I highly recommend you go read the Predict thread. LOL

Tommy McClain
 
Brand: Microsoft

Number of chips in the system: 1
Type: System-on-Package (APU + ROPs/EDRAM daughter die)
Memory layout: UMA + EDRAM on a daughter die with ROPs
Amount of memory and types: 8 GB of DDR4 (2400 MT/s, 256-bit), 32 MB of EDRAM (819.2 GB/s internal, 102.4 GB/s to the main die)
Mass storage solution: HDD
Number of SKUs and brief description: 2
Price(s): $349, $399

CPU provider: AMD
Which architecture and ISA: Jaguar modified with 2x128-bit FMA units instead of FADD+FMUL
Number of cores: 8
Clock speed: ~1.6 GHz

GPU provider: AMD
Number of SIMD: 12 CU (GCN 2.0)
Number of ROPs: 16
Clock speed: 800 MHz
 
im going to keep it generic and stay with what i said 6+ months ago:

both will have something along the lines of a single SOC

8 cores ( steamroller based) ~3.0-3.5 ghz
Full HSA
960 shaders ~700-800mhz (1.6tf)
48 MTU's
16 ROPs

total SOC power 130-150watts

on the memory side i have no idea, some form of stacked, or edam ram + DDR3 or just straight GDDR5.
 
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