I Can Hazwell?

Grall

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Chinese site Chiphell has dredged up some Haswell slides by plumbing the depths of the interwebs - or something. Some interesting tidbits appear, such as:

* New socket for desktops - AGAIN; LGA 1150.
* Desktop CPUs rated up to 95W TDP.
* ULV CPU variant uses multi-chip module with platform hub and CPU on the same substrate; 1.5mm thickness; rated at 15W TDP.
* Thunderbolt support listed as a bulletpoint (unknown if integrated into chipset, and if so into which variants.)
* More reductions in power useage, and so on.
 
Chinese site Chiphell has dredged up some Haswell slides by plumbing the depths of the interwebs - or something. Some interesting tidbits appear, such as:

* New socket for desktops - AGAIN; LGA 1150.
* Desktop CPUs rated up to 95W TDP.
* ULV CPU variant uses multi-chip module with platform hub and CPU on the same substrate; 1.5mm thickness; rated at 15W TDP.
* Thunderbolt support listed as a bulletpoint (unknown if integrated into chipset, and if so into which variants.)
* More reductions in power useage, and so on.

Ggggrrrrrrrrrrrr, Intel and sockets....
 
edp is embedded displayport used in laptops and such devices with internal connections.
ddr3l is special low voltage ddr3 standard that uses 1.35V

I would have asked you guys what those are but then google spoiled all the fun :(

Thankfully though googling on "Fully integrated VR" came up with little meaningful results so I can at least have an excuse to post here. What does that mean? virtual reality? voltage regulators? vaccine for rabies?
 
Thankfully though googling on "Fully integrated VR" came up with little meaningful results so I can at least have an excuse to post here. What does that mean? virtual reality? voltage regulators? vaccine for rabies?

Voltage regulators, I believe.
 
Looks like integrated graphics will get another healthy boost - there are now 3 (GT1 GT2 GT3) options. Interestingly, no plans to offer the fastest option on the desktop, even though the ULV version gets it?
 
Yes, I'd speculate and say "VR" probably refers to voltage regulators. It's been talked about in the past - in Anand presentations and stuff - that integrating those is the next step to increase power efficency since it would allow much faster low-high-low voltage transitions.
 
There should be cost benefits from further integration of board components on-die and better power consumption with more responsive scaling.

One point of curiousity with that is whether it will change the warmup period for AVX mode, where full 256-bit throughput is not acheived until after a warmup period of 70 or so cycles.
I've seen discussion that this could be due to an internal microcode rampup to keep voltage droop in check until the power delivery can catch up.
Maybe it will be less necessary when the voltage regulation is on-chip.

I have questions I hope will be answered in time.
The SB -> IB -> HW TDP divot is curious. What factors lead to IB having a lower TDP than either side? Does the higher level of integration mean somewhat higher chip consumption despite lower overall platform draw?
Does the integrated VR mean less ability by board partners to differentiate based on wacky custom VRM specs?
Will the on-die VR have a lower voltage ceiling than current enthusiast boards permit?
 
One point of curiousity with that is whether it will change the warmup period for AVX mode, where full 256-bit throughput is not acheived until after a warmup period of 70 or so cycles.
I've seen discussion that this could be due to an internal microcode rampup to keep voltage droop in check until the power delivery can catch up.
Maybe it will be less necessary when the voltage regulation is on-chip.
Isn't that why Intel moved to physical register file organisation, precisely to avoid the heavy power load by the widened internal data paths?
 
A PRF reduces general power consumption, but the AVX units do more work in 256 bit mode versus the regular 128.
If the core's voltage levels are currently adjusted to suppply 128-bit mode adequately, the sudden addition of twice as many vector ALUs executing could pull them below safe levels.
A possible fix is to have the chip emit a startup sequence of ops so that the full load from the ALUs is delayed until the power delivery system can catch up.

This is why I wonder if moving the voltage regulators on-die could speed up the process because additional power is much closer and more responsive than before.
 
I think IVB 77W TDP to HSW TDP of 95W is probably dictated by number of transistors used in each design. Both of them are 22nm tri-gate monsters, but I expect HSW to have significantly more trannies deployed as this is new core with possibly even more cache + AVX2.
It can also indicate that Intel leaves themselves door open to eventual 6-core version without hitting TDP wall imposed by too weak motherboard VRM's.
 
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Those TDP numbers surely contain the efficiency losses from the integrated VRs. No idea how efficient such design can be, but possibly at full load ca. 10W could be generated by the VR.
 
There should be cost benefits from further integration of board components on-die and better power consumption with more responsive scaling.

One point of curiousity with that is whether it will change the warmup period for AVX mode, where full 256-bit throughput is not acheived until after a warmup period of 70 or so cycles.
I've seen discussion that this could be due to an internal microcode rampup to keep voltage droop in check until the power delivery can catch up.
Maybe it will be less necessary when the voltage regulation is on-chip.

I have questions I hope will be answered in time.
The SB -> IB -> HW TDP divot is curious. What factors lead to IB having a lower TDP than either side? Does the higher level of integration mean somewhat higher chip consumption despite lower overall platform draw?
Does the integrated VR mean less ability by board partners to differentiate based on wacky custom VRM specs?
Will the on-die VR have a lower voltage ceiling than current enthusiast boards permit?
Well I always believe the TDP of IVY due to the frequency
Intel has kept Performacne 2 level quad-core CPU TDP at 95W for a long time since Q6600 95W Version.
 
Isn't that why Intel moved to physical register file organisation, precisely to avoid the heavy power load by the widened internal data paths?

You still have to support the datapath width through pipeline registers. The move to a PRF gets rid of various queues having to contain the operand data but not the arithmetic pipe.

And that's still a lot of power for a 256-bit datapath, especially for the multipliers.
 
The higher TDP may just be from the fact that they're moving to 6 or 8 cores; the fact that their mobile parts have a lower TDP probably means we're still getting better efficiency per core as usual.
 
The TDPs are for ULV, mobile, and desktop ranges, which top out at 4 cores. Perhaps something is waiting in the wings, but it seems 4 Haswell cores can manage to hit 95W if need be.
 
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