Wii U hardware discussion and investigation *rename

[Cyan]

Hard numbers finally. My life is now complete.

That's interesting, that might explain why they ditched the PS3 and Xbox 360 version of Project Cars and why they are still working on the WiiU version.

Sure the WiiU is not overambitious with its hardware but there have to be important differences compared to the PS3 and Xbox 360, taking into account the 7 years gap.

 

[3dilettante]

I remember reading that Xenos' daughter die was clocked at 2Ghz to achieve those rates. That would then only require a 128-bit connection to the main GPU and 1024-bit internal with the ROPs. I think that's a more realistic setup.

Here is a link from this forum: http://beyond3d.com/showthread.php?t=20082

The eDRAM clocked at 2 GHz?
Post-release information indicates clocks at a quarter (edit: was eighth, don't know why I wrote that) of that.

 

[AlNom]

Sure the WiiU is not overambitious with its hardware but there have to be important differences compared to the PS3 and Xbox 360, taking into account the 7 years gap.

1GB for title memory is probably the main boon I would think.

 

[Grall]

Could very easily have been 1.75GB at least, since Nintendo doesn't use the 1GB they reserved for shit.

 

[Megadrive1988]

I do remember that Xenos' daughter die internal eDRAM bandwidth to the ROPs was 256 GB/sec, but only 32 GB/sec external bandwidth to the parent shader core.

 

[Gipsel]

I remember reading that Xenos' daughter die was clocked at 2Ghz to achieve those rates. That would then only require a 128-bit connection to the main GPU and 1024-bit internal with the ROPs. I think that's a more realistic setup.

Here is a link from this forum: http://beyond3d.com/showthread.php?t=20082

Maybe you should have linked Dave Baumann's article about Xenos on B3D .

I do remember that Xenos' daughter die internal eDRAM bandwidth to the ROPs was 256 GB/sec, but only 32 GB/sec external bandwidth to the parent shader core.

Yes. That's what I wrote, too.

 

[pch]

As far as i know:
32 GB/s is GPU to eDRAM bandwidth -it is actually 64bit bus just double rate so two accesses per clock cycle and yes, eDRAM is @ 2GHz.

 

[3dilettante]

Why were the pixel and sample rates not four times higher than what has been documented?
Were the ROPs on the eDRAM on a different clock multiplier?

 

[pch]

I think i should be more clear:
Xenos is a two chip design,GPU and northbridge on one die(call it parent) and daughter die where 10MB of eDRAM is(which also include FSAA, Alpha, ZLogic and Stencil logic),the link between between the parent and daughter die is clocked at 2GHz.The link is on 64bit bus(DDR),10MB eDRAM sits on 1024bit interface on this die(hence 256 GB/s memory bandwidth to eDRAM).

 

[Exophase]

I think i should be more clear:
Xenos is a two chip design,GPU and northbridge on one die(call it parent) and daughter die where 10MB of eDRAM is(which also include FSAA, Alpha, ZLogic and Stencil logic),the link between between the parent and daughter die is clocked at 2GHz.The link is on 64bit bus(DDR),10MB eDRAM sits on 1024bit interface on this die(hence 256 GB/s memory bandwidth to eDRAM).

You're both right and you're both wrong. http://www.cis.upenn.edu/~milom/cis501-Fall08/papers/xbox-system.pdf

The external interface between the GPU and the eDRAM die is a high clocked bus at 1.8GHz/28.8GB/s (not the oft-quoted 32GB/s, unless they updated it). The internal bandwidth is provided by 4 20Mbit macros clocked at 500MHz. I'd consider them 512-bits wide each and not 1024-bits. You get a read/modify/write but it's only presented on the bus as one item, and this is the same as all conventional DRAMs where reads are destructive and implicitly followed by writes.

 

[Fourth Storm]

You're both right and you're both wrong. http://www.cis.upenn.edu/~milom/cis501-Fall08/papers/xbox-system.pdf

The external interface between the GPU and the eDRAM die is a high clocked bus at 1.8GHz/28.8GB/s (not the oft-quoted 32GB/s, unless they updated it). The internal bandwidth is provided by 4 20Mbit macros clocked at 500MHz. I'd consider them 512-bits wide each and not 1024-bits. You get a read/modify/write but it's only presented on the bus as one item, and this is the same as all conventional DRAMs where reads are destructive and implicitly followed by writes.

Thanks for clearing that up, Exophase. That seems to settle it.

I'm curious, is running the bus at a speed greater than the RAM itself a common practice? Why don't we see more of this? What are the limitations?

 

[Exophase]

I'm curious, is running the bus at a speed greater than the RAM itself a common practice? Why don't we see more of this? What are the limitations?

Yes, most commodity DRAMs with external interfaces are much slower and wider internally than they appear on the bus. That's why a transaction burst needs several cycles.

 

[Fourth Storm]

Yes, most commodity DRAMs with external interfaces are much slower and wider internally than they appear on the bus. That's why a transaction burst needs several cycles.

Ah, I see what you're talking about. Cheers.

 

[Grall]

It's sad commentary on the wiiu when this thread ends up being more about xbox than its namesake...

 

[Esrever]

Why does wikipedia say the wii u gpu have 480 SPs?

 

[Lalaland]

Because it's Wikipedia and anyone can edit it regardless of knowledge of the topic. Never rely on Wikipedia for anything other than general overviews of a subject (or any other encyclopedia for that matter).

 

[Fourth Storm]

It appears the editor is none other than our own eyeofcore!

 

[Shifty Geezer]

Because it's Wikipedia and anyone can edit it regardless of knowledge of the topic. Never rely on Wikipedia for anything other than general overviews of a subject (or any other encyclopedia for that matter).

Unless they provide sources you can corroborate.

It appears the editor is none other than our own eyeofcore!

He's not 'our' eyeofcore. Eyeofcore was evicted because he's most definitely not one of 'us'.

 

[creaks]

Why does wikipedia say the wii u gpu have 480 SPs?

Because its wiki, any fanboy can edit it. Does anyone have ANY salvagable information from this 'project cars' blurb, preferrably in its original state, and not compromised by 'the telephone game' wringer the internet has put it through? I feel like some valuable yet highly time sensitive information has slipped through our fingers.

On that note, id like to ask a question of one of the other leaks of the time period. How each vliw5 block in the supposed alu's (2 simd banks, 16x5) was paired with 4 gpr's? Thats ati for temporary registers yes? Isnt that an excessive amount of memory? Wouldnt that typically be more of an amount you use for a larger amount of shaders? Considerably larger? Assuming there is any truth at all, what beneficial purpose could this serve? Back burner for high dependency waiting? I know running out of registers sucks, but isnt that some serious overkill? Or is it just goofy to the point of being an obvious faux?

 

[bgassassin]

Because its wiki, any fanboy can edit it. Does anyone have ANY salvagable information from this 'project cars' blurb, preferrably in its original state, and not compromised by 'the telephone game' wringer the internet has put it through? I feel like some valuable yet highly time sensitive information has slipped through our fingers.

On that note, id like to ask a question of one of the other leaks of the time period. How each vliw5 block in the supposed alu's (2 simd banks, 16x5) was paired with 4 gpr's? Thats ati for temporary registers yes? Isnt that an excessive amount of memory? Wouldnt that typically be more of an amount you use for a larger amount of shaders? Considerably larger? Assuming there is any truth at all, what beneficial purpose could this serve? Back burner for high dependency waiting? I know running out of registers sucks, but isnt that some serious overkill? Or is it just goofy to the point of being an obvious faux?

Here is the piece that I have about that. GPRs per SIMD - 256 vec4s (4 x 32-bit components)

Also for those interested here is another post I made elaborating a little more on the 192 threads.

http://www.neogaf.com/forum/showpost.php?p=89811956&postcount=699