Wii U hardware discussion and investigation *rename
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It is. You need more than just bit cells to build an DRAM array. Someone quoted the numbers for TSMC (with a comparably sized cell). You can obviously easily (more than) double the needed space.
in this example it's x2.5 between cell size and complete DRAM array size
http://ieeexplore.ieee.org/xpl/logi...re.ieee.org/xpls/abs_all.jsp?arnumber=5872231
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Dominik D
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Argh, my mistake.I said that already and asked for other ideas.
Personally I see little benefit in 24bit floats given that comparable consoles work just fine at 16bit. 12bit floats or fixed-point values would be interesting but I'm not sure developers would want to deal with those (but lower-precision arithmetics would fit well with the low-power concept as min10float in DX11.1 should prove).Hasn't memory been a bottleneck for powerful CPUs?
Maybe Nintendo figured it wasn't necessary to invest in a more powerful CPU if
the memory would become a bottleneck for it. The CPU and Ram are in balance.
Thats why maybe that one developer stated:
The issue with memory bandwidth isn't just the CPU, in fact it's primarily the GPU.
Even with EDRAM the textures have to come from main memory, most of the recent performance captures I've seen for high end GPU's they are limited by texture memory bandwidth, not ALU's, and they have > 10x the bandwidth that the WiiU has.
The EDRAM alleviates the frame buffer bandwidth, and I'll be nice and assume it can be used for intermediate buffers, but it's still going to be an issue.
If the CPU is indeed the 3 enhanced Broadway's @1.6GHz or so, it's going to be an issue for some games regardless of the memory subsystem.
Even with EDRAM the textures have to come from main memory, most of the recent performance captures I've seen for high end GPU's they are limited by texture memory bandwidth, not ALU's, and they have > 10x the bandwidth that the WiiU has.
The EDRAM alleviates the frame buffer bandwidth, and I'll be nice and assume it can be used for intermediate buffers, but it's still going to be an issue.
If the CPU is indeed the 3 enhanced Broadway's @1.6GHz or so, it's going to be an issue for some games regardless of the memory subsystem.
Almost every dev from Namco to Koei to Ninja Theory is pointing the finger of blame squarely at the CPU. I think it's because the low bandwidth memory pool is not an issue. I can't tell you why, but if it was then developers would have said something by now. Historically Nintendo are known for engineering good efficient memory solutions into their consoles.
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Or if you listen to the resident devs here, they are notorious for over designing their memory solution.
Devs here have pointed out multiple time that as both GC and Wii CPU had a L2 cache the inclusion of embedded ram for the CPU was not necessary, it could have been replace by more ram off chip.
I think it is getting more and more obvious that Nintendo engineering capability are going down / executive hinder the capability of their teams to come with the best solutions.
Mize made a good point about it and if memory serves right is has Ph D and works in the field of semi conductor (/ runs his own company).
Gekko and Broadway were always out of order.
And the person who started the Broadway rumour has been pretty reliable so far. He's said that's what it's described as in the dev documents.
They are not exactely out of order, there is a catch to that, I don't remember exactely, may be something about only the first stages of the pipeline being able to be fed out of order / the tech guys here are going to make you a proper answer, sorry for the fail attempt though those CPU are not out of order as say the celeron in the first xbox.
I wasn't aware of this. Do you have links to old posts? Because everything I've read says the chips are out of order, even PPC 750 docs on IBM's site.
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The point of the out of order is the beginning of the pipeline store the instructions & the data,and if both of them available,and there is no dependency then execute the instruction,even if that is not the oldest one.
http://en.wikipedia.org/wiki/Out-of-order_execution
The key concept of OoO processing is to allow the processor to avoid a class of stalls that occur when the data needed to perform an operation are unavailable. In the outline above, the OoO processor avoids the stall that occurs in step (2) of the in-order processor when the instruction is not completely ready to be processed due to missing data.
The benefit of OoO processing grows as the instruction pipeline deepens and the speed difference between main memory (or cache memory) and the processor widens. On modern machines, the processor runs many times faster than the memory, so during the time an in-order processor spends waiting for data to arrive, it could have processed a large number of instructions
The effectiveness of out of order execution depends a lot on implementation. (And of course what kind of code we're dealing with, and how well scheduled it is by the compiler.) Of course, the PPC750 was fairly lightweight in the resources it devoted to OoO execution, by Intels Ivy Bridge standards. How that relates to whatever the hell is in the WiiU is anybodys guess.
Additionally, as it says in the quote from Wikipedia:"The benefit of OoO processing grows as the instruction pipeline deepens and the speed difference between main memory (or cache memory) and the processor widens." Unless I misremember, the PPC750 had 5 pipeline stages.... couple that with a lowish clock and the extremely sympathetic memory subsystem on the WiiU. (Large caches that are fast compared to the core, and even implied access to the eDRAM on the GPU) It simply doesn't need to be very sophisticated, so chasing the last percentages probably wouldn't be worth the price in complexity and power draw.
Now, die size alone, Anandtech:33mm2 at IBM 45nm, makes it clear that we aren't dealing with Broadway - the Gekko was 40mm2 on 180nm which, assuming linear scaling, would mean 2.5mm2 on 45nm. Scaling is never linear, but the WiiU is four times larger than three Geckos shrunk together (and remember that's not just the cores but three times the IO circuitry as well). So if we are indeed dealing with enhanced Broadway cores it's impossible to tell just what enhanced means outside of multiprocessor support, BUT we can definitely say that there is die area enough to modify them fairly heavily. Frankly, the disparity in approximated and real die areas are enough for me to take the "enhanced Broadway" with a grain of salt.
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