loekf
Regular
Nobody....
Sorry for the engineers still working there, but ST-Ericsson is dead now that ST wants to jump ship.
ST-Ericsson Nova A9600: dual-core ARM A15, PowerVR Series 6
- Thread starter rektide
- Start date
Nobody....
Sorry for the engineers still working there, but ST-Ericsson is dead now that ST wants to jump ship.
" It integrates a quad-core Cortex-A9 processor capable of operating at up to 2.5-GHz clock frequency at peak performance, but also capable of operating down at 0.6-V to conserve power. This is a direct result of using an FDSOI manufacturing process."
http://eetimes.com/design/communica...ST-Ericsson-shows-FDSOI-smartphone-processor-
NathansFortune
Regular
Seems pretty outdated. Still no sign of A9600, does it even exist any more?
D
Deleted member 13524
Guest
You really think they'd get 5000 DMIPS from a single core running at 0.6V? If that was the case, I guess Intel would be very worried about STE incredible process technology
The block diagram of the Db8580 part depicts the "eQuad" CPU as comprising 4 overlapping squares?
The narrative also says "
each processor core can operate as an industry-leading high performance core, running at up to 2.5Ghz in the case of the NovaThor L8580, or a very low-power core running at 0.6V."
You really think they'd get 5000 DMIPS from a single core running at 0.6V? If that was the case, I guess Intel would be very worried about STE incredible process technology
So it can reach 500MHz at 0.6V right? From what I can tell, Saltwell on Medfield has a vmin of 0.7V at 600MHz. It's a pretty big core compared to what a Cortex-A9 on 28nm would be so this sounds quite competitive.
Of course it'll be interesting to see what the rest of the voltage curve looks like. Clover Trail's datasheet specifies a Vcore of 0.3V to 1.2V. The low end of that is probably not for a normal operating mode. For comparison, Exynos 5's CPU core voltage goes up to 1.275V for 1.7GHz.
Indeed, although what's perhaps most surprising is just how good Intel's 600MHz at 0.7v really is - from David Kanter's graph at RWT, that does seem accurate. And that's before FinFET... While I'm not convinced Intel's process gives them any cost/area advantage at all, it's clear that it does give them a very big power consumption advantage and that's what allows Atom to be competitive with A9.
From a bit of Googling for relevant code repositories, Tegra 3 cannot go below 0.9v (although there are deleted entries for 0.850v and 0.875v - was it unstable?) and the frequency there is between 680MHz and 1GHz depending on SKU/binning. The LP core can do 294MHz at 1.0v (higher voltage since it's a LP process): http://nv-tegra.nvidia.com/gitweb/?...3;hb=3bb1e9ff9b7302d3c13a27fd24eea6e5968ff7cb
As for Krait, it looks like MSM8960 Pro (Krait v2) can do 384MHz at 0.85v on 28LP (like Intel but unlike NVIDIA iirc, they also have a separate L2 voltage rail): https://github.com/sakuramilk/sc06d...f7893bd502/arch/arm/mach-msm/acpuclock-8960.c
Anyhow, ST-Ericsson's numbers are the very best in the ARM world. It's an impressive achievement and I sincerely hope it gives them the design wins they so badly need!
I couldn't find the full voltage table in the 15 seconds I looked, but the datasheet says "1.35 GHz @ 1.1 V/1.7 GHz @ max 1.3 V" - so it looks like it's heavily overvolted to hit their performance targets, and might be significantly more power efficient (or at least less inefficient
) at 1.35GHz/1.1v.If ST-E doesn't take off with these parts I hope the technology can be continually developed and licensed to other parties at a reasonable price. It sounds much more impressive than I expected.
Is it possible that Intel is sacrificing density at all to reach these low vmin levels for the CPU core? I don't really know anything about the possible trade-offs that one can make here. I know they get a ~ 20mV reduction by using a separate power rail for the L2 cache. Qualcomm appears to be doing this too. I wonder if the ST-E chip is as well - I'm actually not sure if it's an option for either Cortex-A9 (which would need to handle both rails in the external L2 controller) or Cortex-A15 (which would need to take them both internally into the cluster).
I wonder how much the 32nm Samsung process used is leakage optimized like TSMC 28LP is.
That core voltage I gave is what the Linux kernel lists on Chromebook. Anandtech gave the listing but here it is from my Chromebook as well:
I tried finding if anything is measuring and reporting actual voltage but gave up :/
Is it possible that Intel is sacrificing density at all to reach these low vmin levels for the CPU core? I don't really know anything about the possible trade-offs that one can make here. I know they get a ~ 20mV reduction by using a separate power rail for the L2 cache. Qualcomm appears to be doing this too. I wonder if the ST-E chip is as well - I'm actually not sure if it's an option for either Cortex-A9 (which would need to handle both rails in the external L2 controller) or Cortex-A15 (which would need to take them both internally into the cluster).
I wonder how much the 32nm Samsung process used is leakage optimized like TSMC 28LP is.
That core voltage I gave is what the Linux kernel lists on Chromebook. Anandtech gave the listing but here it is from my Chromebook as well:
Code:
exophase@tangent:~$ dmesg | grep ARM
[ 0.000000] CPU: ARMv7 Processor [410fc0f4] revision 4 (ARMv7), cr=10c5387d
[ 0.000000] EXYNOS5: ARMCLK=1700000000, CDREX=800000000, ACLK400G3D=533000000
[ 0.066628] hw perfevents: enabled with ARMv7 Cortex-A15 PMU driver, 7 counters available
[ 1.207915] VDD_ARM : L0, 1275000 uV
[ 1.209437] VDD_ARM : L1, 1225000 uV
[ 1.210935] VDD_ARM : L2, 1187500 uV
[ 1.212402] VDD_ARM : L3, 1125000 uV
[ 1.213862] VDD_ARM : L4, 1100000 uV
[ 1.215285] VDD_ARM : L5, 1075000 uV
[ 1.216675] VDD_ARM : L6, 1050000 uV
[ 1.218059] VDD_ARM : L7, 1037500 uV
[ 1.219406] VDD_ARM : L8, 1025000 uV
[ 1.220732] VDD_ARM : L9, 1000000 uV
[ 1.222037] VDD_ARM : L10, 975000 uV
[ 1.223337] VDD_ARM : L11, 962500 uV
[ 1.224587] VDD_ARM : L12, 950000 uV
[ 1.225838] VDD_ARM : L13, 937500 uV
[ 1.227051] VDD_ARM : L14, 925000 uV
[ 1.228272] VDD_ARM : L15, 912500 uVI tried finding if anything is measuring and reporting actual voltage but gave up :/
loekf
Regular
Appearently they now announced the L8580 @ CES
http://www.stericsson.com/products/L8580.jsp
Built-in LTG/3G modem. Quad Cortex A-9 (@ 2.5 GHz max) + single PowerVRSGX544. VDD for the A9s can be as low as 0.6 V.
No mention of any design-in.
http://www.stericsson.com/products/L8580.jsp
Built-in LTG/3G modem. Quad Cortex A-9 (@ 2.5 GHz max) + single PowerVRSGX544. VDD for the A9s can be as low as 0.6 V.
No mention of any design-in.
Nebuchadnezzar
Legend
https://github.com/AndreiLux/Perseus-S3/blob/master/arch/arm/mach-exynos/cpufreq-5250.c#L163
Code:
/* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10 */
{ 0 }, /* L0 */
{ 0 }, /* L1 */
{ 0 }, /* L2 */
{ 0 }, /* L3 */
{ 0 }, /* L4 */
{ 0, 1300000, 1275000, 1287500, 1275000, 1275000, 1262500, 1250000, 1237500, 1225000, 1225000 }, /* L5 */
{ 0, 1250000, 1237500, 1250000, 1237500, 1250000, 1237500, 1225000, 1212500, 1200000, 1200000 }, /* L6 */
{ 0, 1225000, 1200000, 1212500, 1200000, 1212500, 1200000, 1187500, 1175000, 1175000, 1150000 }, /* L7 */
{ 0, 1200000, 1175000, 1200000, 1175000, 1187500, 1175000, 1162500, 1150000, 1137500, 1125000 }, /* L8 */
{ 0, 1150000, 1125000, 1150000, 1125000, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000 }, /* L9 */
{ 0, 1125000, 1112500, 1125000, 1112500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500 }, /* L10 */
{ 0, 1100000, 1075000, 1100000, 1087500, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500 }, /* L11 */
{ 0, 1075000, 1050000, 1062500, 1050000, 1062500, 1050000, 1050000, 1037500, 1025000, 1012500 }, /* L12 */
{ 0, 1050000, 1025000, 1050000, 1037500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500 }, /* L13 */
{ 0, 1025000, 1012500, 1025000, 1012500, 1025000, 1012500, 1000000, 1000000, 987500, 975000 }, /* L14 */
{ 0, 1012500, 1000000, 1012500, 1000000, 1012500, 1000000, 987500, 975000, 975000, 962500 }, /* L15 */
{ 0, 1000000, 975000, 1000000, 975000, 1000000, 987500, 975000, 962500, 962500, 950000 }, /* L16 */
{ 0, 975000, 962500, 975000, 962500, 975000, 962500, 950000, 937500, 925000, 925000 }, /* L17 */
{ 0, 950000, 937500, 950000, 937500, 950000, 937500, 925000, 925000, 925000, 912500 }, /* L18 */
{ 0, 937500, 925000, 937500, 925000, 937500, 925000, 912500, 912500, 900000, 900000 }, /* L19 */
{ 0, 925000, 912500, 925000, 912500, 925000, 912500, 900000, 900000, 887500, 887500 }, /* L20 */Voltage depends on ASV/adaptive scaling voltage group that gets assigned to the CPU on characteristics/criteria which are fused onto the chip during manufacturing which determine the quality of the chip. A higher ASV means a higher quality chip.
Samsung uses a very large amount of voltage groups for different quality chips;
But you need to realize something: they use adaptive body bias, and in this case mostly reverse body bias to control the transistor thresholds. ABB is also controlled depending on chip ASV, so they change the transistor threshold in another.
What Samsung does is that they dynamically raise RBB by quite a lot in the lower frequencies, this raises the transistor threshold, making very low voltages not possible. But main power drain at low frequencies is not dynamic leakage but static leakage. By raising the reverse body bias they achieve very low static leakage.
In the higher frequencies and also on worse quality chips, they lower the RBB voltage (Raising it over VDD is called forward body bias / FBB) in comparison to VDD which lowers the transistor voltage threshold, this raises the static leakage, but since the higher frequencies are interactive through DVFS, and dynamic leakage is absolutely dominant here, they can lower power consumption or/and recuperate on bad quality chips which otherwise wouldn't certify for their designed frequency. You can see this in the above table for ASV 2-5, VDD voltages doesn't change but ABB voltage does.
My point is: low VDD doesn't mean much anymore nowadays. A chip with a bit higher VDD and also high transistor threshold through RBB can consume less power than an equivalent chip with low VDD and a low transistor threshold.
And another thing: People can usually undervolt on average by 100mV without issues. Different manufacturers may have different safety margins (Threshold voltage varies by that much due to external temperature). On the 4412 we're undervolting by 200mV on the lowest frequencies on average. I've been running my chip for half a year at 712.5mV at the bottom freqs.
Last edited by a moderator:
Just because the maximum frequency is at 2.5GHz it doesn't mean that manufacturers will actually use necessarily such a high frequency. It may very well end up at 2.2 or 2.3GHz in final products.
As for the 2nd question I'd dare to speculate that given the frequency difference between 2.5 and 1.7GHz, they could break even at least in some case scenarios. However what's more important to watch in this case is perf/mW IMHO.
The L8580 strikes me mostly as an upper mainstream SoC. If perf/W is as good as ST promises it to be, it could do quite well.
As for the 2nd question I'd dare to speculate that given the frequency difference between 2.5 and 1.7GHz, they could break even at least in some case scenarios. However what's more important to watch in this case is perf/mW IMHO.
The L8580 strikes me mostly as an upper mainstream SoC. If perf/W is as good as ST promises it to be, it could do quite well.
Hard to say how good it will be in Android due to vendor specific Dalvik optimizations and some benchmark cheats, but in SPECint2k single A15 core = 1.9x - 2x A9 considering ARM data - http://eetimes.com/ContentEETimes/Images/ARM7.jpg
Also A15 is 2x of Krait considering intel SPECint data - http://www.anandtech.com/show/6340/intel-details-atom-z2760-clovertrail-for-windows-8-tablets
and Anand Nexus4 vs Nexus10 results, which should be comparable considering the same browser and Android ver
http://images.anandtech.com/graphs/graph6425/51291.png
http://images.anandtech.com/graphs/graph6425/51292.png
http://images.anandtech.com/graphs/graph6425/51299.png
http://images.anandtech.com/graphs/graph6425/51294.png
A15 is 87% faster then Krait with the same software, or 77% faster if scaled back to 1.5 Ghz
I'm drawing conclusions for devices with same software - Nexus4 and Nexus10, they are both Android 4.2 with Chrome browser. It's pretty straightforward CPU benchmarks for devices with same software
Thanks!
so depending of the benchmark a quadcore A9 could be roughly as fast as a Quadcore A15 with 1,0-1,8GHz
All these java script benchmarks are single threaded, so core count more than 1 is useless here, second - these results are not 100% comparable for different devices due to different browsers with different java script engines(performance is highly software dependent), that's why I'm comparing only Nexus10 vs Nexus4 with same browser
Nebuchadnezzar
Legend
All those benchmarks excluding Browsermark which does some rendering on the side, are single-threaded. Capping the CPU to single core has very little effect on the scores.
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