AMD: Southern Islands (7*** series) Speculation/ Rumour Thread
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That would equal just 8 CUs (512 vALUs) and probably 32 TMUs, I doubt that would be faster than Barts on a lot of workloads, irrespective of the efficiency gains as long as AMD does not increase the clocks significantly.
If that's true we should be expecting at least 32 CU's. In which case it should rape everything.
http://www.hardware.fr/news/11648/afds-architecture-futurs-gpus-amd.html
Today. Looking forward to it, nom nom!
I just wanted to cite that too. Hardware.fr goes on to speculate about at least 30 CUs (with half speed DP
), so in the same ballpark as your guess. From the presentation, the number of CUs should be divisible by 4, though. What about 40 CUs to really gain the high ground? Let's see what would come out of this:
32 CUs = 2048 vALUs (+ 32 scalar ones) = 4096 flop/cycle => 3.5 TFlop/s @ 850 MHz
Sounds reasonable for the next 28nm high end. Maybe they are aiming at 4TFlop/s (975 MHz) for the fastest part to claim at least a 50% increase in raw flops compared to Cayman. If all works out, this could easily mean a blunt doubling of typical gaming performance, in corner cases maybe even a factor of 3-4.
This may have been made more clear elsewhere and I missed it, but I wonder how much of the scalar pipe and arbitration logic was already present in the sequencer blocks and thread engine in current chips, just not exposed to the outside world. At the very least, some of that hardware would be repurposed and made available to the software stream.
The CU is no longer capable of 4 simultaneous ALU op issues, but this is compensated for by having 4-cycle execution. Basically, there is a 3-cycle spin-up period of successive vector issues before we see the same utilization as a best-case fully-packed VLIW instruction.
This is probably compensated for by better utilization and the removal of certain latency penalties related to clause switches and other contributors spin-up latency that was present but not explicitly mentioned.
The vector ALU and register system strikes me as taking Cayman SIMD and putting it on its side.
Instead of a 16 lane 4-way ALU cluster SIMD with a 4-banked register file, we have 4 16 lane SIMDs and 4 register files.
This removes the rather baroque register file read system employed in the VLIW system, or at least hides it in hardware.
What does it do for multi-lane special ops, though?
The CU is no longer capable of 4 simultaneous ALU op issues, but this is compensated for by having 4-cycle execution. Basically, there is a 3-cycle spin-up period of successive vector issues before we see the same utilization as a best-case fully-packed VLIW instruction.
This is probably compensated for by better utilization and the removal of certain latency penalties related to clause switches and other contributors spin-up latency that was present but not explicitly mentioned.
The vector ALU and register system strikes me as taking Cayman SIMD and putting it on its side.
Instead of a 16 lane 4-way ALU cluster SIMD with a 4-banked register file, we have 4 16 lane SIMDs and 4 register files.
This removes the rather baroque register file read system employed in the VLIW system, or at least hides it in hardware.
What does it do for multi-lane special ops, though?
Are you refering to me? Because that's not what I was saying. I wonder about how the well the chip could handle software rendering model.
If not... well just ignore my post
Completely off.
The scalar unit is not exposed to user. Compute wise, it is more like fermi than lrb,
Yes, as a mental image it looks to me like they transposed the op<->reg matrix.
My guess is that transcendentals are processed like in fermi, no multi lane magic to get them to work.
http://www.pcper.com/news/Graphics-Cards/AMD-Fusion-Developer-Summit-2011-Live-Blog
Few more details being discussed now.
Few more details being discussed now.
Yeah, it shares a lot with Fermi but takes it another step further. A CU resembles an SM and even has similiar throughput (64 scalar ALUs @ core clock vs 32 scalar ALUs @ 2x core clock). Should be much easier to compare the two architectures going forward.
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