AMD: R9xx Speculation
- Thread starter Lukfi
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Man from Atlantis
Veteran
so RPE is AMD's GPC's.. it means twice triangle power twice tessellation power than previous 5xxx..
RPE?
My idea: One RPE is one "ultra threaded dispatch processor" and one rasterizer (and one Shader/TMU block)..
That would mean Turks is the slowest chip, which doesn't make much sense but it's just name so who knows
edit:
IMO it looks like this
Caicos - Barts - Cayman
160x4 - 320x4 - 480x4
32 - 64 - 96
16 - 32 - 48 (could be 32 too but 48 would "fit" the rest better)
1 - 2 - 3
Jawed
Legend
Which is very much the same as Evergreen, only called "shader engine".
DavidGraham
Veteran
It could , however , it is more logical that a RPE is like a GPC , because it scales perfectly with core count :
Caicos : 1 RPE = 640 SPs
Barts : 2 RPE = 1280 SPs (640x2)
Cayman : 3 RPE = 1920 SPs (640x3)
Yeah. But the problem is still the same: 32 TMUs and 160x4 TPs - this can't work (RV770 style). Or R600 is back.
The problem is you know what nvidia did with Fermi. Yet you think that AMD will do the same.
DavidGraham
Veteran
Makes me wonder .. why blur the rest of the specs ? I understand the need for blurring the superior and inferior parts , but why the specs ?As long as the slides are sufficiently blured we can make sensible configurations out of them, instead of calling fake due to inconsistent numbers
At least that took care of the wavefront problem , it sets now at 64 as it should be .
Don't forget the TMUs. 96 TMUs and 30 SIMDs - this can't work.
Or we go back to the R600 style but this time with 2 clocks latency.
So one RPE has than: one TMU-SIMD (32 TMUs) and 5 32-way-SIMDs.
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DavidGraham
Veteran
Wasn't R600 just like Rv770 ? i.e: it used 4 shader clusters (80 SPs each) , with a texture quad block for each cluster ?
Jawed
Legend
That's no different from 64 TMUs and 320x4 ALU lanes.
In both cases it seems an RPE consists of 10 SIMDs. With 32 TMUs.
Which would imply TMUs are shared within an RPE by all the SIMDs ...
... or something along the lines of the patents I've been talking about, where TMUs are shared by SIMDs. The patents talk about a "processor" producing two filtered results independently and also sharing texel data (unfiltered texels, not texel results) amongst L1s, with 2 TMUs seemingly sharing an L1. Those two concepts would appear to tally with this peculiar setup.
R600 shares only results, I think, not original texel data (or, if you prefer, texel data isn't shared amongst L1s, only amongst L2s). Though it would be funny if a ring-bus appeared.
Barts Pro, presumably, has SIMDs turned off. It presumably also has TMUs turned off. So with SIMDs being much larger than TMUs, it's likely that while only 1 quad-TMU per RPE is turned off, 2 or more SIMDs would be turned off.
e.g. 1024 ALU lanes and 56 TMUs.
I have to admit I've got a queasy feeling about the "non-integer-multiple" SIMD:quad-TMU thing going on here.
This is the main difference: The R600 design had a decoupled TMU-SIMD. So the R600 had five SIMDs: one TMU-SIMD and four Shader-SIMDs.
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DavidGraham
Veteran
I see , thanks for the heads up .
Is there a possibility that we are tackling the wrong side of the problem ? Cayman could have 24 SIMDS (80SPs each) and maintain the right texture arrangement . (4x24 = 96) ?
I know the wavefront problem would persist , but what is more likely ? a change in wavefront (with subsequent load on the compiler possibly degrading performance ) or a change in texture quads arrangement ? what is the least harmful option ? doesn't TMU sharing add latency and conflicts?
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