AMD: R9xx Speculation

That's a fairly poor article since it doesn't even question the huge gap in 40nm bulk that GF's roadmap paints.
Are you referring to the gap between 5LP and 40G.


It makes a useful baseline for what AMD's plans once were - hence my earlier exposition of SI and NI. Obviously no one believes TSMC's optimism about 28nm.
Partially. That TSMC roadmap appears to be ~18 months ahead of NI/SI product planning, so it's only partially reasonable. But yeah, 28nm this year seems closer to vapor than wafer.
 
... and TSMC is particularly bad at complex chips on new cutting edge processes.
What is so particular about it? Is TSMC worse in this respect than others? Or have complex chips much lower yields than what could be estimated from the overall process defect density?

I doubt it will make a difference to SI. SI will be designed to hit the sweet spot strategy and ship on time with the highest performance on he process available, whilst Nvidia will still be getting the bugs out of the manufacture of the massive top-end Fermi.
What kind of bugs do you have in mind? Are you suggesting that they need to do something different for Fermi than for their other 40nm chips?

Can Nvidia do a dumb shrink of Fermi?
Can ATI do a dumb shrink of RV870? Would it be easier or more difficult than Fermi? Why?
Isn't a shrink down to the next node going to mean a redesign, especially if TSMC has gone from a gate first to gate last?
Which aspects of a design does you expect to be impacted by going from a gate first to gate last process?
I think a Fermi shrink is going to be quite a lot more complicated that just a simple shrink of the same design.
Why would that be so? Why would one design (say, RV870) be less complicated to shrink than another (say Fermi)?

Personally, I think the main problem is the design ethos at Nvidia - they keep going for massive chips on new processes that arn't ready for them.
Design ethos? What does that even mean?

You have this way with words that makes it sound like you know things...
 
IBM's forays into foundry work haven't always been great, either.
Nvidia had IBM fab some of its GPUs at one point, and there were indications of trouble.

I would hold off on thinking GF is somehow going to be better, given the number of satisfied foundry customers it currently has at any non-x86 node is still 0.
That AMD's then-internal fabs had a better high-performance process than TSMC is not a guarantee they won't have troubles as a foundry. x86 margins and the option for way more bins allowed for much more variation and somewhat lower yields than more price-restricted products.

GF needing to stick with gate-first because that's what IBM decided is not something we can hand-wave away, when other players with HIKMG processes are going gate-last or went gate-last to start with.
Intel's great PMOS performance and reputedly much better control over variability (see that the V word comes up) are at least in part credited to gate-last.
Gate first has had problems with the metal being subjected to thermal and process steps that can seriously impact this, and there's no statement that GF has found a way to totally lick that problem.

There was a link to an eetimes article in another thread on the gate-first/last debate, and how some of the advantages of gate-first were lost anyway in the 45-28 nm range, and gate-first may need to be abandoned anyway for 22nm and below. Most of the partners in the IBM process alliance do not want gate-first, typically the customers whose process needs more closely match a foundry customer than IBM's big iron market.
 
If anyone (or anything) has ONE single name for one of the S.I. chips, i'd be very grateful
Do you mean one of the rumored code names (Cozumel, Ibiza, Kauai)? They appeared september last year and came from error and debug messages ATI forgot in the driver binaries (at least that's my source and I had no success in finding an earlier reference to those names).

From the same strings one could deduce that the Northern Islands line of GPUs loses the possibility to execute some instructions in the t unit (but the 5 slot VLIWs appear to stay with us). Maybe it gets more like a specialized SFU and also loses the MADD, so ATI won't count them for the total SP number in the future (would fit the rumors of reduced SP count, but it would apply only to NI, not to SI, if Charlie is right about SI basically using the Evergreen shaders).

Btw., I wrote that in september/october last year already, I even mentioned Southern Islands in a German forum post back then :LOL:
 
IBM's forays into foundry work haven't always been great, either.
Nvidia had IBM fab some of its GPUs at one point, and there were indications of trouble.

I would hold off on thinking GF is somehow going to be better, given the number of satisfied foundry customers it currently has at any non-x86 node is still 0.
That AMD's then-internal fabs had a better high-performance process than TSMC is not a guarantee they won't have troubles as a foundry. x86 margins and the option for way more bins allowed for much more variation and somewhat lower yields than more price-restricted products.

GF needing to stick with gate-first because that's what IBM decided is not something we can hand-wave away, when other players with HIKMG processes are going gate-last or went gate-last to start with.
Intel's great PMOS performance and reputedly much better control over variability (see that the V word comes up) are at least in part credited to gate-last.
Gate first has had problems with the metal being subjected to thermal and process steps that can seriously impact this, and there's no statement that GF has found a way to totally lick that problem.

There was a link to an eetimes article in another thread on the gate-first/last debate, and how some of the advantages of gate-first were lost anyway in the 45-28 nm range, and gate-first may need to be abandoned anyway for 22nm and below. Most of the partners in the IBM process alliance do not want gate-first, typically the customers whose process needs more closely match a foundry customer than IBM's big iron market.

It seems to me that gate-first is a primary cause of channel length variation @40nm and below. If so, then there is definitely advantageous to go with TSMC rather than GF below 40nm.

I am curious to know how much effect this change alone would have in a design process. If you knew about it from the start (either as a dumb shrink or as a new chip otherwise) , then it should have minimal impact at most. Your layout extraction would prolly change, but it shouldn't be a big deal in grand scheme of things.

BTW, does the gate first/last impact SOI and bulk equally?
 
Do you mean one of the rumored code names (Cozumel, Ibiza, Kauai)? They appeared september last year and came from error and debug messages ATI forgot in the driver binaries (at least that's my source and I had no success in finding an earlier reference to those names).

From the same strings one could deduce that the Northern Islands line of GPUs loses the possibility to execute some instructions in the t unit (but the 5 slot VLIWs appear to stay with us). Maybe it gets more like a specialized SFU and also loses the MADD, so ATI won't count them for the total SP number in the future (would fit the rumors of reduced SP count, but it would apply only to NI, not to SI, if Charlie is right about SI basically using the Evergreen shaders).

Btw., I wrote that in september/october last year already, I even mentioned Southern Islands in a German forum post back then :LOL:

I'm curious, why are those codenames Southern Islands? They are all in the northern hemisphere.
 
TSMC pulled the 28nm ahead by a quarter. A dumb shrink of Fermi might be enough time (and be small enough) to fix the heat/clocks/yields and upstage ati.

I'll believe they pulled it ahead by a quarter when they actually deliver. Last I heard they had to switch their whole transistor stack.

GF is ~1Q behind TSMC in process roadmap, according to original 32 nm plans. 28 nm is prolly next year. That does put a bit of strain on the claims that NI wafers were on display @CES2010. ;)

Well, could just be that GF is actually showing a real roadmap and TSMC is fantasy.
 
After the latest shenanigans, me too. :yep:
But why would you have ~year gap between having wafers back and a hard launch?

First wafers to production for a process can be up to 2 years. And there is always the possibility that GF wasn't exactly honest with what it was.
 
First wafers to production for a process can be up to 2 years. And there is always the possibility that GF wasn't exactly honest with what it was.

So when a foundry says that is ready for risk production, how much delay for volume shipping is to be expected?
 
Thinking about it some more I'm starting to question the timing of 32nm. I've realised, contrary to my earlier thoughts, that 32nm might have been treated as a "half node" by TSMC, an optical shrink. But I'm unsure, to be honest, because 40nm was originally a half-node of 45, so 32 would have been a full-node from 45.

In a sense TSMC has shifted its full nodes by half a node downwards (45 became 40nm) and seemingly dropped half-nodes (no 32nm from 40nm). I suppose this depends on whether "half node" is defined by the ability to use an optical shrink, or if it merely reflects steppings that are substantially less than a 2x density increase.

Jawed

People are finally starting to see it my way. Thank God for both of X-bits' articles yesterday, they clear up what's been evident for months. From SiON being a failure at <45nm to GF canceling 32nm bulk to compete with TSMC at 28nm; those articles are quotable victories. :)

40nm was what TSMC 'aimed' for when producing the 45/40nm node. While designs were taken for 45nm, all manufacturing was switched to 40nm as that planning made it possible to pursue on equal ground (minus the fact SiON gets steadily worse at <45nm, which they obviously didn't factor in). Since it became (or was planned) as their full node, everything moved a (half) step forward, and TSMC has said as-much since 40nm production. I fully believe 32nm to have been an optical shrink, or a half-node, as nothing was going to be changed other than what usually changes on a half-node. It was still SiON-only, and was again ALWAYS destined to fail for all that reason. HKMG is crucial to <45nm processes for all the reasons TSMC's 40nm is messed up and 32nm would've been worse. Transistor variability, leakage, etc. I could link to articles with engineering folks saying this since before 40nm production, but that would be irrelevant at this point. TSMC has always planned to finally fix their next full node, 28nm, which is far too late to start on HKMG. Arguments about what is and what isn't a full-node are semantics. You can go by what they call and based a full node on (40,28,22) or what 'standards' call a full node (45,32,22). What TSMC did is what TSMC did. The whole SiON fiasco coupled with their first HKMG risk production starting supposedly end of Q3 when GF/Intel tested/are testing them for an eternity before production truly makes me question WTF TSMC is doing. Are they incompetent and refuse to learn from their proven optimistic failures, or just trying to put on a nice PR face of lies? I'm largely leaning towards the former. They're obviously trying stay ahead, but if they continue those decisions above any semblance of practicality, they are going to implode once GF is in the game.

At any rate, I like your hypothetical roadmap/plan. Sounds reasonable and makes sense from a process point of view, although I would then ask why AMD's roadmaps (leaked from those projector presentations) showed NI at 32nm. I, at this point, feel 32nm was the calm before the 28nm MCM storm, with the large 32nm part being redesigned for use in single/mcm configs for the mid-range and performance sectors, but I have a feeling that's an area of possibility where you and I still respectfully disagree. ;)

Edit: @ RPG: I believe it is six months.
 
From the same strings one could deduce that the Northern Islands line of GPUs loses the possibility to execute some instructions in the t unit (but the 5 slot VLIWs appear to stay with us). Maybe it gets more like a specialized SFU and also loses the MADD, so ATI won't count them for the total SP number in the future (would fit the rumors of reduced SP count, but it would apply only to NI, not to SI, if Charlie is right about SI basically using the Evergreen shaders).
Hmm, or maybe there is no T lane and all its instructions are "emulated" across the remaining lanes, e.g. integer MUL could be done just like a double-precision MUL.

Jawed
 
BTW, does the gate first/last impact SOI and bulk equally?
I suppose AMD's Llano GPU designers and low-end GPU designers would eventually have the best answer for that.
I don't think there are many examples of somewhat equivalent products running on both.

One interesting question for PD-SOI is the history effect does have an affect on the size of certain circuits like analog circuits and sense amps.
In that case, variability in switching history is counteracted by somewhat larger contact transistors that impose a density and switching penalty.

Gate-first, while it is claimed by some to have some better density than the more restrictive gate-last method, might inject more variability in those same transistors.
I wonder if the register-heavy SIMDs designed for bulk turned out to be a bit fatter when they were put on an SOI substrate for Llano, and whether gate-first improved or worsened that situation.
 
At any rate, I like your hypothetical roadmap/plan. Sounds reasonable and makes sense from a process point of view, although I would then ask why AMD's roadmaps (leaked from those projector presentations) showed NI at 32nm.
Since I posted that I've been wondering exactly the same thing. Only thing I can say is that those pictures are much newer than my "guesstimated roadmap of yesteryear".

At one point I was even wondering if NI and SI are the wrong way round :p

Also, Hecatoncheires doesn't refer to islands as far as I can tell, so, erm...

Jawed
 
People are finally starting to see it my way. Thank God for both of X-bits' articles yesterday, they clear up what's been evident for months. From SiON being a failure at <45nm to GF canceling 32nm bulk to compete with TSMC at 28nm; those articles are quotable victories. :)

40nm was what TSMC 'aimed' for when producing the 45/40nm node. While designs were taken for 45nm, all manufacturing was switched to 40nm as that planning made it possible to pursue on equal ground (minus the fact SiON gets steadily worse at <45nm, which they obviously didn't factor in). Since it became (or was planned) as their full node, everything moved a (half) step forward, and TSMC has said as-much since 40nm production. I fully believe 32nm to have been an optical shrink, or a half-node, as nothing was going to be changed other than what usually changes on a half-node. It was still SiON-only, and was again ALWAYS destined to fail for all that reason. HKMG is crucial to <45nm processes for all the reasons TSMC's 40nm is messed up and 32nm would've been worse. Transistor variability, leakage, etc. I could link to articles with engineering folks saying this since before 40nm production, but that would be irrelevant at this point. TSMC has always planned to finally fix their next full node, 28nm, which is far too late to start on HKMG. Arguments about what is and what isn't a full-node are semantics. You can go by what they call and based a full node on (40,28,22) or what 'standards' call a full node (45,32,22). What TSMC did is what TSMC did. The whole SiON fiasco coupled with their first HKMG risk production starting supposedly end of Q3 when GF/Intel tested/are testing them for an eternity before production truly makes me question WTF TSMC is doing. Are they incompetent and refuse to learn from their proven optimistic failures, or just trying to put on a nice PR face of lies? I'm largely leaning towards the former. They're obviously trying stay ahead, but if they continue those decisions above any semblance of practicality, they are going to implode once GF is in the game.
But as has been pointed out GF's gate first approach for 28nm, even with HKMG, is hardly the best choice. Belatedly, yes, but finally TSMC seems to be taking the better path here. Who makes it first to volume remains to be seen.

Edit: @ RPG: I believe it is six months.
Well, then 2Q11 is the best bet for 28nm parts.
 
Hmm, or maybe there is no T lane and all its instructions are "emulated" across the remaining lanes, e.g. integer MUL could be done just like a double-precision MUL.
As you need some lookup tables for a SFU (transcendentals, div, sqrt and so on, most use some kind of a LUT), I really doubt it. And as I said, I've read from it, that there still is a t unit.

Btw., the possibility to do a 32bit integer multiply with the combined xyzw ALUs was already mentioned in an Evergreen presentation. But a documentation for that is still missing (as the mul_int24 instruction in IL).
 
Hmm, or maybe there is no T lane and all its instructions are "emulated" across the remaining lanes, e.g. integer MUL could be done just like a double-precision MUL.

Jawed

The transcendental stuff will be much harder to emulate that way.
 
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