NVIDIA Fermi: Architecture discussion
- Thread starter Rys
- Start date
Maybe the performance hit is caused by the extra shading on the new surfaces created by the tessellation?
What other DX11 features does it use?
I don't think tessellation increases overdraw much so pixel shading workload shouldn't go up (although ALU utilization might fall due to smaller triangles).
Tesselation creates small triangles that ruin the rasterization efficiency as it works in quads, and smaller triangles have a smaller chance to completely fill 2x2 quads. Lots of triangles may also cause stalls if the setup engine isn't fast enough... and there are some other issues, but we've discussed it in different threads already. I think it was AMD 8xx speculation and the topics about the Unigine DX11 benchmark itself.
Jawed
Legend
I think it does some kind of ambient occlusion too, though I now realise that AO might be a part of the D3D10 and DX9 paths
So unless there's something else I guess it is in fact a pure tessellation/no-tessellation difference on D3D11 hardware.Jawed
http://www.semiaccurate.com/2009/11/02/nvidia-finally-gets-fermi-a2-taped-out/
Nvidia finally gets Fermi A2 taped out
Nvidia finally gets Fermi A2 taped out
Nvidia finally gets Fermi A2 taped out
http://www.semiaccurate.com/2009/11/02/nvidia-finally-gets-fermi-a2-taped-out/
http://www.semiaccurate.com/2009/11/02/nvidia-finally-gets-fermi-a2-taped-out/
That's some very interesting info, although Charlie definitely makes a few rather strange mistakes:
1) 'assuming that Nvidia parked a few wafers to speed up the next hot lot' - uhhhh, what? You claim they parked a truckload of risk wafers and that if a metal fix isn't enough, then they'll lose gazillions of money. Those ARE the same wafers they'll use a few of for the next hot lot! You can't have it both ways!
2) 'From there, if the risk wafers did not need to be scrapped, you are about six weeks from production silicon, best case.' - errr, unless you *do* believe that A2 is nearly certainly good (or that if it isn't all your risk wafers are useless anyway), in which case you are six weeks from production silicon, best case, starting *from the tape-out date*!
3) 'It would be safe to read into this that the A2 stepping is not going to cut it, and an A3 spin is on the cards.' - unless they've got a major bug that prevents them from using an entire subsystem which they assume is also bugged but which they cannot debug without first fixing the former major bug (very very unlikely/ridiculous scenario and I'd assume they'd still try to get it right via a lot more simulation effort), then this is complete hogwash. You don't tape-out an A2 if you know you'll need an A3 to launch. You just don't; it would be completely retarded.
4) 'Another bit of anecdotal evidence is that there is no sign of the other four GT300 variants taping out.' - uhm... So he's expecting NVIDIA to tape-out at least one derivative within *days* of the big brother's respin? Even with the best execution ever (which Charlie certainly wouldn't assume of NV), that'd be rather optimistic.
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So here's the *most optimistic scenario* assuming the respin taped-out in W42: hot lots back in early W46, production lots in W48, review samples sent in W49, hard launch in W51.
And for balance's sake, here's the ultra-pessimistic scenario: respin taped-out in W43, hot lots in W47, realized major bug in W48/49, completely new tape-out in W51, hot lots back in W6, respin tape-out in W11, hot lots based on new risk wafers back in W15, production lots in W17, review samples sent in W19, hard launch in W21. And yes, that does get us to late May 2010 - which is why it's really, really important that A2 works and the risk wafers aren't lost.
1) 'assuming that Nvidia parked a few wafers to speed up the next hot lot' - uhhhh, what? You claim they parked a truckload of risk wafers and that if a metal fix isn't enough, then they'll lose gazillions of money. Those ARE the same wafers they'll use a few of for the next hot lot! You can't have it both ways!
2) 'From there, if the risk wafers did not need to be scrapped, you are about six weeks from production silicon, best case.' - errr, unless you *do* believe that A2 is nearly certainly good (or that if it isn't all your risk wafers are useless anyway), in which case you are six weeks from production silicon, best case, starting *from the tape-out date*!
3) 'It would be safe to read into this that the A2 stepping is not going to cut it, and an A3 spin is on the cards.' - unless they've got a major bug that prevents them from using an entire subsystem which they assume is also bugged but which they cannot debug without first fixing the former major bug (very very unlikely/ridiculous scenario and I'd assume they'd still try to get it right via a lot more simulation effort), then this is complete hogwash. You don't tape-out an A2 if you know you'll need an A3 to launch. You just don't; it would be completely retarded.
4) 'Another bit of anecdotal evidence is that there is no sign of the other four GT300 variants taping out.' - uhm... So he's expecting NVIDIA to tape-out at least one derivative within *days* of the big brother's respin? Even with the best execution ever (which Charlie certainly wouldn't assume of NV), that'd be rather optimistic.
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So here's the *most optimistic scenario* assuming the respin taped-out in W42: hot lots back in early W46, production lots in W48, review samples sent in W49, hard launch in W51.
And for balance's sake, here's the ultra-pessimistic scenario: respin taped-out in W43, hot lots in W47, realized major bug in W48/49, completely new tape-out in W51, hot lots back in W6, respin tape-out in W11, hot lots based on new risk wafers back in W15, production lots in W17, review samples sent in W19, hard launch in W21. And yes, that does get us to late May 2010 - which is why it's really, really important that A2 works and the risk wafers aren't lost.
Just a for instance ... they might have a game stopping bug in the top metal layers, but have a clock limiting one lower in the stack.
ihamoitc2005
Veteran
Lots of transistors
I am not sure a chip like this is smart my friends. It is better to have many simpler chips that one very large chip. This will be very expensive for manufacturing without a revolution in manufacturing technology.
Maybe they are hoping for this revolution.
If it is cheap to manufacture and receive then there can be software revlution on top of this chip and maybe that is what Nvidia is hoping.
This is not a great chip for the home computer but better for server side rendering and other remote computing.
I am not sure a chip like this is smart my friends. It is better to have many simpler chips that one very large chip. This will be very expensive for manufacturing without a revolution in manufacturing technology.
Maybe they are hoping for this revolution.
If it is cheap to manufacture and receive then there can be software revlution on top of this chip and maybe that is what Nvidia is hoping.
This is not a great chip for the home computer but better for server side rendering and other remote computing.
Groo The Wanderer
Regular
No mistakes, you just seem to have several fundamental misunderstandings of the process. Allow me to attempt to fix that.
Depending on where the risk wafers are parked, it shaves some time off. I cut the time almost in half in my estimates, from about 7 weeks to 4. It could be less. What misunderstanding?
You don't put in production silicon until you can test your fixes. Given the nature of the problems NV has, not simple logic problems, I would think they would be mighty stupid to not test A2 before they pulled the trigger on $50M worth of wafers. Then again, I do think they are indeed mighty stupid, so you may be right.
That said, the problems that A1 had are not easy, if they were simple logic bugs, it would not have taken 7 weeks do do what they should have done in 1-2 weeks. I know what the problems they were trying to fix are, it sure sounds like you don't. If you knew, you would not be saying what you are saying.
Also given how fundamentally broken the chip is in A1, (think they showed only simulated graphics for fun?) there is a lot of room for masking of other bugs.
Short story, it could be production from A2 tapeout. I really really doubt it.
You obviously don't have any idea the nature of the problem(s) they were trying to fix. My real question is if they can get it right in A3.
Actually, what I said is "If A2 would have done the trick, there would have been much more movement at TSMC on the variants, and there does not seem to be." Question for you Arun, do you think that when a chip tapes out, a courier shows up at TSMC with a bunch of HDs labeled "NV Sooper-sekrit chip dezine", or possibly a few masks, or do you think there is a little collaboration between the two sides? If it is the former, then you would be right. If it is the latter, then go re-read what I wrote, and stop being totally selective on your quoting.
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Interesting question for you Arun, if you know A2 will work, why pay for the hot lots?
-Charlie
Wut?
From samples to launch in 3 weeks? That's your "pessimistic" analysis?
I suppose if manufacturers completely skip on quality assurance/product certification that could be possible, but otherwise I would guess they'd like to know if their cards actually WORK or not within specified parameters such as temps, volts etc, work with all currently available PCIe hosts and run the software they're supposed to run...
SiliconAbyss
Newcomer
Correct if I'm wrong, but wasn't the 4 month window shorter than AMD expected and was more or less a best case scenario for them?AMD's "Samples to Launch" for RV870 was over 4 months, for Mobile Parts it will be over 7 Months
