I'm not sure if it was mentioned here, but the Power7 seems to have 4 DP FP-units per core. Source: http://arstechnica.com/hardware/new...er7-twice-the-muscle-half-the-transistors.ars
So as it looks like 128 DP-GFlops. Seems a lot!
Ars had a old article about the eDRAM from IBM: http://arstechnica.com/old/content/2007/02/8842.ars
one other point:
The Power7 seems to be a new "breed" of PIM or "Processing in Memory". So maybe IBM will now advance the POWER CPUs in this direction. The large eDRAM cache could point in this direction.
Link to a zettaflops presentation about PIM: http://www.zettaflops.org/PES/3-AdvArch-Kogge.pdf
So as it looks like 128 DP-GFlops. Seems a lot!
Ars had a old article about the eDRAM from IBM: http://arstechnica.com/old/content/2007/02/8842.ars
IBM says that it has a 65nm prototype eDRAM running with 1.5ns latency and 2ns random cycle time—speeds that are competitive with current SRAM.
one other point:
The Power7 seems to be a new "breed" of PIM or "Processing in Memory". So maybe IBM will now advance the POWER CPUs in this direction. The large eDRAM cache could point in this direction.
Link to a zettaflops presentation about PIM: http://www.zettaflops.org/PES/3-AdvArch-Kogge.pdf
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