I wouldn't say it's academic. It may be when the framerates are so high but there are plenty of games which need a lot of CPU power these days and if that requirement keeps going up (which it will) the weaker CPU in todays academic tests is the CPU that is too slow to play tomorrows games.
I wouldn't say it's academic. It may be when the framerates are so high but there are plenty of games which need a lot of CPU power these days and if that requirement keeps going up (which it will) the weaker CPU in todays academic tests is the CPU that is too slow to play tomorrows games.
Please, try to design your own multi-gigaherz, multi-pipeline OOE processor which still has to have full SW compatibility to quite quirky 30 year old processors.
When you have done this, you may have an answer to your question.
And.
Bulldozer has not been released. We have seen NO benchmarks which give results we can trust. We have seen "leaks" and fakes, some numbers completely made up and some numbers run with beta-hardware which have had some performance-improving features off, and clock speeds have also been lower than final hardware.
Lets wait until we have some number with the real final hardware, running at final clockspeeds, until making any stupid judgements.
DarthShader
Regular
I don't understand, why are you guys believe anything that comes from Obrovsky? He's a troll and attention whore.
The [H] post is recent, the links it reposts are old, and I'm pretty sure these have come up before.
AMD's shift to a more automated flow, and the consequences of that choice have been admitted.
BD's stripped down cores and longer pipeline basically keep it in place in a world where it does not seem to believe it can count on a having money, which includes subsidiary assumptions that it may not have as good a process or as heavily customized logic.
The speed racer design in BD probably saw some of its theoretical clock eaten up by these details.
Fusion designs have a dominant part of their logic taken up by an ASIC.
It may be interesting to see if Maier's analysis is as relevant now as it was during his tenure.
One question is that AMD looks to be positioning itself to be a second-fiddle value proposition, so could it sustain the style of design he espoused, as design complexity increases?
Another is the question of the payoff for that heavy level of engineering he is writing the eligy for.
Are the benefits as significant at current and upcoming nodes as they were back in the K8 days, and are the costs any higher?
AMD's shift to a more automated flow, and the consequences of that choice have been admitted.
BD's stripped down cores and longer pipeline basically keep it in place in a world where it does not seem to believe it can count on a having money, which includes subsidiary assumptions that it may not have as good a process or as heavily customized logic.
The speed racer design in BD probably saw some of its theoretical clock eaten up by these details.
Fusion designs have a dominant part of their logic taken up by an ASIC.
It may be interesting to see if Maier's analysis is as relevant now as it was during his tenure.
One question is that AMD looks to be positioning itself to be a second-fiddle value proposition, so could it sustain the style of design he espoused, as design complexity increases?
Another is the question of the payoff for that heavy level of engineering he is writing the eligy for.
Are the benefits as significant at current and upcoming nodes as they were back in the K8 days, and are the costs any higher?
There's some slight detail in the empty space in the center. There's probably miscellaneous logic in there that either didn't show very well or AMD made sure did not show well.
At least some of it could be IO controllers and the interconnect between the modules and L3 partitions.
The ring of blank space around each module could be attributed to the power gating transistors.
I need to go over what SB and BD dedicate for uncore area when I have the time to see if one or the other is more area-efficient.
At least some of it could be IO controllers and the interconnect between the modules and L3 partitions.
The ring of blank space around each module could be attributed to the power gating transistors.
I need to go over what SB and BD dedicate for uncore area when I have the time to see if one or the other is more area-efficient.
You're speaking of the Orochi "4 modules / 8 cores" thingy? That's damned huge
The official die-size is confirmed at 315 sq.mm. Not much different from what was speculated already.
The six core 32nm Gulftown die is 32% smaller, for comparison.
EDIT found the picture at semiaccurate. It's still damned big.
EDIT OK the picture was blocked at my job but usually I've something stating so.
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There is a cross-bar interconnect wiring between the L3 slicesright in the middle of the die, but it's still considered a waste. SNB, for example, routes its ring-bus wires beneath the transistor logic, and I guess this is due to more robust hand tuned layout, where AMD cut some corners with automatic placement process.
A crossbar is also physically more complex and can be more congested than a more straightfoward ring bus.
In Intel's case, I think the ring bus goes over the L3 cache slices, not the logic.
Intel's distributed ring bus protocol would also not be sufficient for AMD's crossbar, so more centralised arbitration logic could take up space in that section as well.
Given the higher complexity, there may have not have been room to put all the wires over the cache.
In Intel's case, I think the ring bus goes over the L3 cache slices, not the logic.
Intel's distributed ring bus protocol would also not be sufficient for AMD's crossbar, so more centralised arbitration logic could take up space in that section as well.
Given the higher complexity, there may have not have been room to put all the wires over the cache.
I haven't seen many details on the BD crossbar. It seems possible AMD's crossbar could be more capable than Nehalem's, given the server focus of BD.
It does look like Intel does devote a measurable amount of die space in the middle of the L3 to some kind of logic for the interconnect.
It does seem plausible that Intel could engineer more area savings than AMD in this regard, though it does seem like the ring bus takes up less room than that.
It does look like Intel does devote a measurable amount of die space in the middle of the L3 to some kind of logic for the interconnect.
It does seem plausible that Intel could engineer more area savings than AMD in this regard, though it does seem like the ring bus takes up less room than that.
The dual die Interlagos CPU-s will face each other probably trough the side with HyperTransport phy. Could it be that the area till the northbridge is actualy there for the two chips comunication.
Edit: Or just with the aggressive clock gating its the safest place for the wiring.
Edit: Or just with the aggressive clock gating its the safest place for the wiring.
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