That is more an indication that Via cannot engineer its way through process issues, but must skip a process node for a moderate-performance x86 design. An uninspiring result that makes the small team size loom large.
I think the most desired outcome when hitting process problems would be to have the resources to engineer a solution, instead of punting the whole design rollout down a process node and a different fab and negating all tentative design plans by customers.
I think the most desired outcome when hitting process problems would be to have the resources to engineer a solution, instead of punting the whole design rollout down a process node and a different fab and negating all tentative design plans by customers.