And even that is too simple if you wanted to be perfectly honest: G80 can use half the MUL in CUDA and none in 3D, while GT200 can use all the MUL in CUDA but only half in 3D. Yay?
Only the Core 2 numbers should be doubled. They can execute MUL and ADD in parallel while Pentiums only have a single execution port for both (and only half the SIMD width).
The P4 number needs doubling too as it is able to execute 2 MULs and 2 ADDs per cycle (single precision). Having a single execution port for SSEx instructions doesn't become a bottleneck (if the MULs and ADDs are interleaved) as the execution pipes (MUL and ADD) only accepts one 128-bit operation every two cycles.
Wasn't the R300 able to do 4 MADs and 4 ADDs per quad? That should make it 8*4*3. That holds true for R400 and R500 IIRC.
Done that now, cheers.What I found interesting with NV3x was the similar performance of 5200 vs 5600 at the same clock speed, esp. given the ~47m vs ~80m trans difference. (NV36 sorted the VS & clock issues of NV31).
Note that those VS engines aren't "true" Vec5. There's a Vec4 unit and a scalar unit. R200 cannot dual issue an instruction to both at the same time, thus it's irrelevant for a peak flop number. R300-R500 can dual issue to both, however for peak flop it's still irrelevant since it can't dual issue when the vector engine executes a mad (since the encoding of the scalar unit is done in the 3rd source operand field for dual-issue). Scalar unit is limited to 2 source operands (so only mul and no mad) too.
HyperThreading doesn't affect peak performance. It merely lets two threads share the same execution units.
I've heard that claim before, but never found a conclusive confirmation. Indeed having multiple execution units bound to the same port doesn't prevent them from simultaneous interleaved execution, but according to the Intel documentation FP-MUL and FP-ADD are subunits within the same FP execution unit. Subunits have no separate control as far as I know. So the ADDPS and MULPS instructions can't execute simultaneously like that. Interestingly this doesn't apply to the integer SSE instructions. PADDW executes on the MMX-ALU subunit which is part of the MMX execution unit (sharing the same port as the FP unit) while PMULLW executes on the FP-MUL subunit.
I've never had a good answer to that, FWIW; I'm sure the "off-shader" parts were sufficiently different to save a lot of transistors (things like compression but not just that), but still... It might ironically indicate NV30's performance/mm² inefficiency was not where you would expect it to be.
IIRC the subunits can execute different instructions in parallel (i.e. they have separate control). Anyway I can try this theory out as I've got a few P4s lying around, both Northwood and Prescott.
That seems to confirm my memories that the different subunits can execute independently.
Well, this stuff isn't a big secret anymore - you can find all that information here: http://www.x.org/docs/AMD/R5xx_Acceleration_v1.3.pdf. It also has sections covering differences to R3xx and even R2xx (well for VS at least) so you can see how it evolved.mczak: Very interesting, never knew that - cheers!
That would be great, thanks.
No, note that MMX-ALU and FP-MUL are part of different execution units (namely MMX and FP), while FP-MUL and FP-ADD are part of the same execution unit. So it only confirms that execution units bound to the same port can execute independently, not subunits within an execution unit.
Not sure how but running fpmul and fpadd simultaneously should indeed work. From a p4.pdf (found it here: http://www-cse.ucsd.edu/classes/sp02/cse241/p4.pdf)
