Here are my estimates for die usage for GT200 based on the high resolution GT200 die shot:
I've measured areas inside major blocks on the die, ignoring the "shiny" spaces between these major blocks. This is because the shiny spaces vary in size and seem to indicate that there are only metal layers there, no logic. These shiny spaces amount to 38.1mm² of the die, that is 6.5% of the die appears to have no logic nor I/O
We can argue till the cows come home over the per-cluster split between ALUs and TMUs. Irrespective, the important thing to note is that a cluster is ~28.5mm².
On GT300, using 65->40nm scaling, a cluster of the same configuration (3 multiprocessors of 8 MADs, 2 MIs, 1 DP plus 8 TMUs) would be ~10.8mm².
Put bluntly, GT300 should have >3x the ALUs of GT200. ALU:TEX is very likely to increase, e.g. 4 multiprocessors per cluster, with 2 quad-TMUs. NVidia won't be able to reach 1024 ALUs, but I think somewhere in the region of 24 clusters (of 32 single-precision MAD ALUs ) = 768 is quite feasible. That would result in about 305mm² of clusters. Of course this is assuming no changes whatsoever. No increase in DP, no 32KB shared memory, and no other changes. Even after allocating 100mm² to ROPs and MCs (as opposed to 133mm² in GT200) there's still a hell of a lot of die left over, if GT300 is >500mm².
Some other entertaining numbers, just because I can, GT200 versus RV770, normalised to 55nm:
- per single-precision MAD - 0.626mm² v 0.095mm² - 659%
- per single texture result - 0.676mm² v 0.788mm² - 86%
- per single colour write (ROP) - 1.021mm² v 0.808mm² - 126%
- per single Z write (ROP) - 0.128mm² v 0.202mm² - 63%
Jawed
