AMD: R8xx Speculation

How soon will Nvidia respond with GT300 to upcoming ATI-RV870 lineup GPUs

  • Within 1 or 2 weeks

    Votes: 1 0.6%
  • Within a month

    Votes: 5 3.2%
  • Within couple months

    Votes: 28 18.1%
  • Very late this year

    Votes: 52 33.5%
  • Not until next year

    Votes: 69 44.5%

  • Total voters
    155
  • Poll closed .
Because in speculation land, anything is possible.

Soviet Russia must be part of the islands in the northwest then! :eek:



Anyway, nVidia should have a big revamp of their arch ready by 11 that should upset all current reasonable extrapolations. Not saying it's better, but marketing wise it should be radically new. :D
 
40nm RV870 is expected to release next year, are likely to be RV770 released after almost a year after release, that is, July and August of next year.
http://translate.google.com/transla...c/hard/79861.htm&hl=en&ie=UTF8&sl=zh-CN&tl=en


1 year from now - huh!

Sources also said, 40 nm RV870 will be built more transistors than the RV770 will be built in more than 956 million transistors

EDIT: RV870 at 40nm will have more transistors then 55nm-RV770; it should be 2x performance!
 
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So then there will be a rv770 refresh? Seems likely...


Depends on the availability of the 45/40nm Process for GPUs. If the process is only available in spring 2009 then imho it would be foulish to release a refresh of the DX10.1 RV770 only to release a DX11 RV870 a few weeks later.
 
1. ATi 5800 series

12 arrays
512MB/1GB GDDR5
192x5 (960 sp)
c650mhz/782mhz
m4700mhz/5700mhz
16 ROPs
48 TMUs
1.25/1.5 Teraflops
128-bit
75gbps/90gbps
<75W/150W
512MB-1GB GDDR5
$179/$219

...

I don't think they will call it 5800 series for some reason :LOL:
 
The pads are the connections between the die and the package. They have a certain size and cannot be made smaller. So for a given number of connections you need a certain minimum die size to accomodate all of them. The original RV770 design was too small to accomodate a 256-bit bus so they had to add more SIMDs to fill it out a bit and make it big enough. It's a really nice problem to have.
What's the pad pitch nowadays for flip-chip? 100 microns or so? That's 100 pads per mm2 if they really want to. It's more of an economic question than anything else.
 
http://www.fudzilla.com/index.php?option=com_content&task=view&id=8934&Itemid=1

40nm GPU

We don’t know many details about this upcoming 40nm chip, but we do know that RV870 is codenamed Little Dragon. This is a performance chip and it is the base for R800, a dual RV870 card.

Little Dragon is a rather interesting codename and we know that we can expect this card in 2009, possibly even in 1H 2009.

This is definitely going to be one of the first 40nm cards around, at least from ATI’s workshop, and we’ve heard that Nvidia wants to go down the same 40nm path.

Traditionally, ATI was faster in transitioning to new processes, it did so with 65nm and 55nm and it remains to be seen if it can beat Nvidia to 40nm.

Why! ---->possibly? More detail please....
 
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U have to look closer. Everyone talks about RV740 but no one knows whats behind it. So, in ur opinion, what is RV740 really?

And, RV870 codename is not Little Dragon!
 
U have to look closer. Everyone talks about RV740 but no one knows whats behind it. So, in ur opinion, what is RV740 really?
Assuming all of those chips exist and are on 55nm, this would be the most logical roadmap would be:
RV770: 256-bit GDDR5, 16 ROPs, 40 TMUs, 800 SPs
RV740: 192-bit GDDR3, 12 ROPs, 24 TMUs, 480 SPs
RV730: 128-bit GDDR3, 8 ROPs, 16 TMUs, 320 SPs
RV710: 64-bit GDDR3, 4 ROPs, 8 TMUs, 120 SPs
Of course, that's not a given.
 
That sound logical, but imho it would be a bit of an "overkill" for a single lineup. Maybe rv740 is more of a rv8xx chip w/ a rv7xx codename.
 
Assuming all of those chips exist and are on 55nm, this would be the most logical roadmap would be:
RV740: 192-bit GDDR3, 12 ROPs, 24 TMUs, 480 SPs
RV740, I thought was supposed to be RV730 @ 40nm and likely GDDR5 for the time-frame. AMDs small "test chip" for the new process.

RV710: 64-bit GDDR3, 4 ROPs, 8 TMUs, 120 SPs

Fuad gave today some performance numbers, which sound like taken from an AMD slide:
http://www.fudzilla.com/index.php?option=com_content&task=view&id=9043&Itemid=65
I do not think this would be possible with 64-Bit.
 
RV740, I thought was supposed to be RV730 @ 40nm and likely GDDR5 for the time-frame. AMDs small "test chip" for the new process.

This was the impression I had as well, although I like Arun's chip better :LOL:
 
Assuming all of those chips exist and are on 55nm, this would be the most logical roadmap would be:
RV770: 256-bit GDDR5, 16 ROPs, 40 TMUs, 800 SPs
RV740: 192-bit GDDR3, 12 ROPs, 24 TMUs, 480 SPs
RV730: 128-bit GDDR3, 8 ROPs, 16 TMUs, 320 SPs
RV710: 64-bit GDDR3, 4 ROPs, 8 TMUs, 120 SPs
Of course, that's not a given.

Judging from history, 192-bit busses do not seem to be that popular. Otherwise we would have seen at least one or two by now. :smile:
 
Multi-GPU

Concept -> 1 master chip and up to 4 slave chips.

The master chip is like a normal GPU... but with 4 SidePorts.
These SidePorts use the Rambus FlexIO Interface:
· Rambus FlexIO is capable of running from 400 MHz to 8 GHz.
· Contains only 12 lanes (5 lanes are inbound, 7 outbound)
· Theoretical peak I/O bandwidth of 76.8 GB @ 8 GHz (44.8GB out, 32GB in)
· Total bandwidth: 76.8GB/s x 5 SIMD Core (1 internal + 4 "slave chips") = 384GB/s

Q. Why use Rambus FlexIO Interface ?
A. Because AMD can use it (Rambus Signs Patent License Agreement with AMD) and because it's realy fast :
"While Cell’s XDR interface offers over 2x the memory bandwidth of any PC-based microprocsesor, Cell’s FlexIO interface weighs in at 76.8GB/s - almost 10x the chip-to-chip bandwidth of AMD’s Athlon 64." - Anandtech


A picture is worth a thousand words -> HD 5870 Concept
And this is the cards for the other market segments -> HD 5000 Series

A slave chip, or SIMD Core, is made of 8 blocs, for a total of 640 SP (128 SP 4D+1) and 16 TMUs -> picture

HD 5450 -> 640 SP + 16 TMUs (1 master chip)
HD 5650 -> 1280 SP + 32 TMUs (1 master chip + 1 slave)
HD 5670 -> 1920 SP + 48 TMUs (1 master chip + 2 slaves)
HD 5850 -> 2560 SP + 64 TMUs (1 master chip + 3 slaves)
HD 5870 -> 3200 SP + 80 TMUs (1 master chip + 4 slaves)


thumbup.gif

· Need only 2 chips (master/slave) to create a complete series of graphic cards.
· The slave chip is an exact copy of the "SP/TMUs" part of the master chip.
So when you create the master chip, you also create 95% of the slave chip.
· Less time/money needed to create a new series -> 9 month product cycle instead of 12 months.
· Very small chips -> very good yields -> very good price.
· Shared memory architecture ! :p

thumbdown.gif

· The highest memory bandwidth hogs are the ROPs and the Level 2 texture caches, so ATI has physically placed these units next to the memory controllers and used a thousand or so traces to connect them. So, for now, it's impossible to put the RBEs inside the slave chips. Thus, the master chip has to contain enough RBEs for the HD 5870... but this high number of RBEs will be overkill for the HD 54xx/56xx. This is perhaps the major problem with this design.

NOTE: I know that there is a RBE in the first image but I'm too lazy to remove it.
 
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Wouldn't it be impossible to get real-time parallelisation from multiple chips? Bringing Crossfire and its multiple niggles down into the mainstream? Hmmm. Skeptical.
 
Assuming all of those chips exist and are on 55nm, this would be the most logical roadmap would be:
RV770: 256-bit GDDR5, 16 ROPs, 40 TMUs, 800 SPs
RV740: 192-bit GDDR3, 12 ROPs, 24 TMUs, 480 SPs
RV730: 128-bit GDDR3, 8 ROPs, 16 TMUs, 320 SPs
RV710: 64-bit GDDR3, 4 ROPs, 8 TMUs, 120 SPs
Of course, that's not a given.

VR-Zone says RV730 has 32 TMUs. Also Fudzilla came back to his previous statement about RV710 having 120 SPs. Fudo apparently misread something and now it supposedly has 80 SPs instead...
 
I'd rather believe Aruns Speculations on this matter than Fudos or VR-Zones "confimations". ;)
 
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