NVIDIA GT200 Rumours & Speculation Thread
- Thread starter Arun
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Just a guess, but I'd say this layout helps them to better exploit the PCB layers they have. If the chips were placed exactly opposite to each other, it would mean having to route two groups of wires through the same area of the PCB. Whereas with this layout, they put the wires next to each other and they don't need as many PCB layers.
It depends on if the chips are sharing the same channel or not. If you're pairing 2 chips into a 64-bit channel (like R600) you want them on top of each other to share command and address pins. If each chip is an independent 32-bit channel, you need space to route the signals like lukfi says.
Jawed
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NVidia eking-out double precision transcendentals from single-precision coefficients?:
High-speed function approximation
Jawed
High-speed function approximation
Jawed
@fellix:
These are some beautiful renderings. If I may ask, what application did you use for that? Did you do any custom work or just an import? Looks very metallic.
While we´re at it, have a look at it in wireframe mode and concentrate at the area where the GPU is supposed to be connected to the PCB. There are like 3-4 different squares and if you look closely I think you can see how big the GPU is. That however originates from the thought that what we see on the renderings is the IHS in the first place.
These are some beautiful renderings. If I may ask, what application did you use for that? Did you do any custom work or just an import? Looks very metallic.
While we´re at it, have a look at it in wireframe mode and concentrate at the area where the GPU is supposed to be connected to the PCB. There are like 3-4 different squares and if you look closely I think you can see how big the GPU is. That however originates from the thought that what we see on the renderings is the IHS in the first place.
I'm no expert, but since the 8800GTX has 12-way memory and 24 ROPs, is it safe to say that if this rendering is accurate, the GT200 with 16-way memory will have 32 ROPs?So... 16-way memory access?
Now let's speculate on the ROP configuration on that.
Edit:
A more wild guess is that an MCM'ed design would require such arrangement for a "fused" 512-bit bus.
It could just aswell have 16, I mean seriously, is there anything pointing to that we'd need any more ROPs than 16?
Maybe I'm missing something here but doesn't 8 ROP partitions imply 32 ROPs...?
Yes, but has 8 ROP partitions been confirmed anywhere?
Then what would be the point of going to a 512bit bus if they aren't going to use that extra bandwidth?
I believe someone made a comment/statement about the ROPs being the primary variable in respect to needed bandwidth.
NV's current architecture ties ROP partitions into memory controller channels, i.e. 1 partition per 64-bit channel. We've seen mechanical drawings which show 16 GDDR3 memory chips on a single PCB. With 2 memory chips per channel, this gives us a memory interface width of 8x64 = 512-bits. From this information we can deduce that GT200 (or whatever it's called) has 8 ROP partitions, and thus 32 ROPs.
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