trinibwoy's Recent Activity

  1. trinibwoy liked 3dcgi's post in the thread AMD: Navi Speculation, Rumours and Discussion [2019].

    They do share the instruction cache just not the vector L0. Yes

    Jun 5, 2020 at 10:28 AM
  2. trinibwoy replied to the thread AMD: Navi Speculation, Rumours and Discussion [2019].

    That's true for HPC parts but RDNA and "gaming" Turing have the same LDS:ALU ratio of 1KB per FP ALU. They also share the same 4KB LDS...

    Jun 5, 2020 at 2:27 AM
  3. trinibwoy replied to the thread AMD: Navi Speculation, Rumours and Discussion [2019].

    Any chance AMD will drop the confusing “dual compute unit” terminology for RDNA2? It seems the two CUs share an L0 instruction cache and...

    Jun 4, 2020 at 5:51 PM
  4. trinibwoy replied to the thread AMD: Navi Speculation, Rumours and Discussion [2019].

    Lol.

    Jun 4, 2020 at 5:46 PM
  5. trinibwoy liked Ext3h's post in the thread AMD: Navi Speculation, Rumours and Discussion [2019].

    There has been only one ACE since early GCN, and there still only is. What's shown as 2 ACEs is a single core with 2x SMT, and each...

    Jun 2, 2020 at 1:40 PM
  • About Us

    Beyond3D has been around for over a decade and prides itself on being the best place on the web for in-depth, technically-driven discussion and analysis of 3D graphics hardware. If you love pixels and transistors, you've come to the right place!

    Beyond3D is proudly published by GPU Tools Ltd.
Loading...