Recent content by Robbitop

I doubt this would be a too serious bottleneck. It'd only cost a single clock for the RBEs to loop in order to place 4 subsamples per pixel into the framebuffer. What's a single clock compared to maybe a hundred ones for the calculation of a single pixel?

Did you or other chaps at ATI try to play WoW or HL2 on R600? Here is a HL2 Savegame: http://www.keepmyfile.com/download/56cf9c1598001 F.e look at the ground while you walking along the rails. You will notice pretty hefty shimering artifacts. In WoW it is the same. On any texture with high...

Eric why does the MSAA algortihm cost so much frames? The memory interface is much wider than R580, the compression algoritm are better and the ROPs can do more color/z compares than R580. The donwsampling in the shader cannot be the only reason for that. In OGL games we saw some...

I second that. I just forgot to insert the context...typical brainfart, sorry. But as you say practically SRAM has worse latency than a flipflop circuity and DRAM has wore latency than SRAM. So the core statement of mine is correct.

Silent_guy. The numbers of clocks are dependant to the access time in ns relative to the core clock of the ASIC. In case of R600 I took the value of 800 MHz. You are only looking at the access time of a single memory cell. But it takes time to allocate adresses, to find the right data, and...

As you know a clock cycle is a unit for time if you know the dependancy to the clockrate of the ASIC. An of course for things like texture caching and for storing terms for arithmetical operations latency is a problem, which cannot be hidden so easily. I'd not call it foolish but creative...

Not only the pure bandwith is an important criteria for that. The latencies have to be very small. For example: -a read/write access on a flipflop circut is done in a single clock (registers) -a read/write access on sram is done in ~10 clocks -a read/write access on eDRAM is done in ~100-150...

The solution would be to increase the granulartity of the memory controllers. 32/64 bits per channel would be reasonable.

The threaded design surely is a point. I second that. But another is the USC Design and fullfilling the claims of D3D10. And of course the enhancement of the efficiency is very expensive. NV has only 16x Vec8 Units (with very complex control logic for scalar fetches). DAAMIT seems to go the...

But we don't know the count of transistors, are we? ;) I think this is a too much superficial point of view. Just adding transistors without the knowledge the details of the cost about the realisation of D3D10 specs is kind of senseless. Anyway I can't provide this kind of knowledge because I'm...

Per Vec4/5 ALU? I don't see any reason why ATI should not support a 2 : x split, which would allow to do 2x Vec2 operations as well per clock and Vec4/5 (whatever this will be) ALU. But to aquire 2x differenct Vec2 operations for the same quad won't be happen so often.

I doubt that. AFAIK they don't support: -Int format -IEE-754 compliance (specific approximation rules, specific calculation accuracy, specific configuration of the FP format which differs from the former configuration) -fMAD with FP32 -inf/nan with spec. approx -fMAD FP16 w/out denorm...

Tell me some things I don't already know. ;) Facts are: -fullscreen or windowed mode, the fillrate is going down to the expectated value of the selected SSAA mode -windowed the mode runs just fine -in full screen mode the pattern is mest up (but the full amount of samples is used in some...

Actually it is fore sure ;) The fillrate (fullscreen) tests indicate nearly exactly 1/5 or 1/9 of the original fillrate. Maybe the samples are located on each other or something weird.

Usually I use the same resolution as my desktop (TFT user). But in this investigation I used 800 and 1024 for Fullscreen AND window mode, to get sure there is no rendertarget bottleneck. Thank you, man ;) I did the same investigation with my DeltaChrome S8 in the past. The result is quiet...